Abstract: A print control device, a control method of a print control device, and a recording medium storing a program enable easily configuring a peripheral device connected to a printer. A POS terminal that configures peripheral devices connected to a receipt printer has a device configuration selection unit for selecting a configuration of peripheral devices; and a device configuration screen display unit that displays a configuration screen for the peripheral devices based on the selected device configuration. Because a configuration screen for a peripheral device that is not connected to the receipt printer (a configuration screen that is not needed) is not displayed, the risk of creating confusion regarding the configuration of a peripheral device for the user can be reduced.

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Abstract: Systems, methods, and other embodiments associated with a low power audio codec are described. According to one embodiment, an audio codec includes an audio buffer configured to store decoded audio data received from an application processor external to the audio codec. The application processor is configured to decode audio data in a RUN mode. The audio codec is configured to store, in the audio buffer, decoded audio data received from the application processor when the application processor is in IDLE mode and provide the stored decoded audio data to an audio device while the application processor is in a low power mode.

Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

Abstract: A displaying device includes a first storing portion that stores first connection data indicating connection statuses of a plurality of instruments and a controlling system, a second storing portion that stores second connection data indicating connection statuses of a plurality of instruments and an instrument controlling device, a displaying portion that displays the first connection statuses through the first connection data and the second connection statuses through the second connection data, and a display controlling portion that causes the first connection statuses and the second connection statuses to be displayed separately on the displaying portion.

Abstract: For dynamically adjusting write pacing, a calculation module calculates an interval as a maximum threshold for a primary volume divided by a first maximum pacing level for a first importance level. The calculation module further calculates a first pacing level as a number of record sets that have not been mirrored to a secondary volume divided by the interval. The first pacing level is set to the first maximum pacing level if the first pacing level is greater than the first maximum pacing level. The calculation module also selects a first pacing delay associated with the first pacing level from a delay table. A pacing module delays writes for a first channel command word writing to the primary volume by the first pacing delay.

Abstract: According to one embodiment, a media system communicates with an aggregate device that includes multiple media output devices. When providing media data for presentation, the system adjusts for device clock drift by resampling the media data provided to a media output device based at least in part on a device clock rate difference between a device clock of one of the media output devices and a device clock of another of the media output devices.

Abstract: Deterministic message processing in a direct memory access (DMA) adapter includes the DMA adapter incrementing from a sub-head pointer, a sub-tail pointer until encountering an out-of-sequence packet. The DMA adapter also consumes packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer. In response to determining that the sub-head pointer is equal to the sub-tail pointer, the DMA adapter determines whether the head pointer is pointing to the next in-sequence packet. If the head pointer is pointing to the next in-sequence packet, the DMA adapter resets the sub-head pointer and the sub-tail pointer to the head pointer. If the head pointer is not pointing to the next in-sequence packet, the DMA adapter resets the sub-head pointer and the sub-tail pointer to the next in-sequence packet.

Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.

Abstract: A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

Abstract: A method and apparatus for inputting and outputting data by using a virtualization technique are provided. The method includes generating a virtual operating system (OS) for the external device, which is connected to a host, based on OS information stored in the external device, setting a partial area of a storage of the host as virtual storage for the external device, and storing the data in the virtual storage or a memory of the external device in response to a request for inputting and outputting the data from the virtual OS.

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition.

Abstract: M-PHY communications are provided over a mass storage-based interface. Related connectors, systems, and methods are also disclosed. In particular, embodiments of the present disclosure take the M-PHY standard compliant signals and direct them through a memory card compliant connector so as to allow two M-PHY standard compliant devices having memory card based connectors to communicate.

Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.

Abstract: In a method of controlling an accessory device by a mobile computing device, upon being communicatively coupled with the accessory device, the mobile computing device communicates with the accessory device using an accessory communication protocol to receive accessory information, and protocol configuration data associated with a specific application executable on the accessory device. The mobile computing device reconfigures the accessory communication protocol based on the protocol configuration data to obtain a reconfigured accessory communication protocol, and then communicates with the accessory device using the reconfigured accessory communication protocol to control execution of basic functionality and the specific application on the accessory device.

Abstract: Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes. A plurality of nonvolatile memory units may be included with computing nodes, coupled with computing nodes or coupled with input/output nodes. The input/output nodes may be included with the compute cluster or super computer, or coupled thereto. The nonvolatile memory units store data items provided by the computing nodes, and the input/output nodes maintain where the data items are stored in the nonvolatile memory units via a hash table distributed among the input/output nodes. The use of a distributed hash table allows for quick access to data items stored in the nonvolatile memory units even as the computing nodes are writing large amounts of data to the storage system quickly in bursts.

Abstract: A semiconductor memory system may include a plurality of memory devices each configured to have multiple planes, and an access controller configured to access each of the multiple planes corresponding to each of the plurality of memory devices as a unit memory.

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.