Abstract: An apparatus to facilitate matrix multiplication operations. The apparatus comprises multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations on a plurality of multiplicands and perform addition operations on results of the N×N multiplication operations.

Abstract: The illustrative embodiments provide a method, system, and computer program product. In an embodiment, a method includes receiving a set of Pauli observables. In an embodiment, a method includes initializing a measurement basis, the measurement basis comprising a set of Pauli bases equivalent to a number of qubits of a quantum processor. In an embodiment, a method includes creating a list of a set of Bell basis candidates, each of the set of Bell basis candidates configured to measure at least one of the set of Pauli observables. In an embodiment, a method includes selecting a Bell basis candidate from the set of Bell basis candidates. In an embodiment, a method includes reconfiguring the measurement basis to replace a subset of the set of Pauli bases with the selected Bell basis candidate.

Abstract: The present disclosure relates to a method for controlling execution of a GEMM operation on an accelerator comprising multiple computation units, a first memory device, and a second memory device. The method comprises determining an execution manner of the GEMM operation, the execution manner comprising partition information of the GEMM operation and computation unit allocation information of the partitioned GEMM operation; generating one or more instructions to compute the partitioned GEMM operation on one or more allocated computation units; and issuing the one or more instructions to at least one of a first queue and a second queue, which enables at least one of a first local controller and a second local controller to execute the one or more instructions, wherein the first local controller and the second local controller are configured to control data movement between the computation units, the first memory device, and the second memory device.

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.

Abstract: Techniques described herein perform spherical PIP analysis by detecting whether a test ray (defined by a test point (TP) and a point (EP) that is external to a spherical polygon) crosses edge arcs (“edges”) of the polygon based on relative orientations of vertices of the test ray and edges. A classifier vector (CV) for a test ray is calculated based on the cross-product of the TP and the EP. Using the CV, the orientation of each vertex of the polygon with respect to the test ray is determined. Candidate edges having vertices with opposite orientations with respect to the test ray are identified. Crossing edges are determine by calculating CVs for each candidate edge, and determining orientations of the TP and EP with respect to each candidate edge. A set of crossing edges is determined, where the TP and the EP have opposite orientations with respect to each crossing edge.

Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

Abstract: Systems and methods that facilitate motion formalism utilizing quantum computing, to compute matrix operators in terms of commutators between qubit operators and measurements on the quantum hardware, wherein the commutators are computed utilizing symbolic calculus. Embodiments reduce computational cost of generalized eigenvalue synthesis relying on symbolic calculus and parallelization. Embodiments disclosed herein can also develop estimators of excited-states properties, considering constants of motion (e.g. spin) and non-constants of motions (e.g. dipoles, density matrices).

Abstract: Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments enforce sparsity constraints for performing sparse matrix multiply-add instruction (MMA) operations. Deep neural networks can exhibit significant sparsity in the data used in operations, both in the activations and weights. The computational load can be reduced by excluding zero-valued data elements. A sparsity constraint is applied across all submatrices of a sparse matrix, providing fine-grained structured sparsity that is evenly distributed across the matrix. The matrix may then be compressed since a minimum number of elements of the matrix are known to have zero value. Matrix operations are then performed using these matrices.

Abstract: A data processor receives a first set of processor instructions for combining a first matrix with a second matrix to produce a third matrix and generates a second set of processor instructions therefrom by identifying values of non-zero elements of the first matrix stored in a memory of the data processor and determining memory locations of elements of the second matrix. An instruction of the second set of processor instructions includes a determined memory location and/or an explicit value of an identified non-zero element. The second set of processor instructions is executed by the data processor. The second set of processor instructions may be generated by just-in-time compilation of the first set of processor instructions and may include instructions of a custom instruction set architecture.

Abstract: Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.

Abstract: The present invention relates to computing-implemented method and system that improves matrix multiplication efficiency, especially to method and system optimizing matrix multiplication using sparse basis approach. Matrices to be multiplied are organized into specially ordered vectors with zero values, facilitates speed up during linear combination computation or synthesis process.

Abstract: Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

Abstract: A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes a plurality of unit circuits. Each of the unit circuits includes a multiplying-adding circuit, a first register, and a second register. A first input terminal and a second input terminal of the multiplying-adding circuit are respectively coupled to a corresponding first input line and a corresponding second input line. An input terminal and an output terminal of the first register are respectively coupled to an output terminal and a third input terminal of the multiplying-adding circuit. The second register is coupled to the first register to receive and temporarily store a multiplication accumulation result. Wherein, the second registers of the unit circuits output the multiplication accumulation results in a column direction in a first output mode, and output the multiplication accumulation results in a row direction in a second output mode.

Abstract: A signal processing method performed by a processor of a signal processing device and includes: generating a fundamental matrix according to at least one set of fundamental coefficients; generating a phase-shifted matrix according to a predetermined phase shift and the fundamental matrix; and generating an output sequence according to an input sequence and the phase-shifted matrix. The set of fundamental coefficients is used to generate at least one bit of a code sequence, the output sequence is a phase-shifted version of the input sequence being shifted by k cycle(s), and k is the predetermined phase shift.

Abstract: Methods and devices, the method including receiving a matrix of a neural network model; classifying at least a portion of the matrix as a first section based on a first distribution pattern of non-zero elements of the portion of the matrix; and identifying memory addresses of the non-zero elements in the first section of the matrix for loading, according to a first order determined based on the first distribution pattern, the non-zero elements in the first section into one or more vector registers.

Abstract: The disclosure is directed at a method of data compression using inferred data. By determining the number of leading zeroes for each data structure, a general header presenting all leading zeros can be generated and use to compress the data.

Abstract: Example implementations relate to assigning dependent matrix-vector multiplication (MVM) operations to consecutive crossbars of a dot product engine (DPE). A method can comprise grouping a first MVM operation of a computation graph with a second MVM operation of the computation graph where the first MVM operation is dependent on a result of the second MVM operation, assigning a first crossbar of a DPE to an operand of the first MVM operation, and assigning a second crossbar of the DPE to an operand of the second MVM operation, wherein the first and second crossbars are consecutive.

Abstract: Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.

Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.

Abstract: A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.