Abstract: Method and system for a device having a processor module for maintaining a connection with another device are provided. The device includes a timer module having a plurality of timers, where the resolution for each timer is maintained by one or more processor modules; and a timer state module that stores an indicator value for indicating a timer state. A timer is assigned to the connection and the processor module manages the resolution of the timer. The processor module sends a request to the timer module for arming the timer and the timer module sets the timer state as active in a first storage location maintained by the timer state module; and responds to the processor module after the timer is activated. The processor module uses the information in the response for requesting a disarm operation.

Abstract: Systems and methods are disclosed for hardware assisted format changes in a display controller. One embodiment of the invention relates to a format change system comprising a register DMA controller and a register update list. The register update list contains at least one instruction. The register DMA controller is adapted to obtain and use at least one instruction to configure at least one display pipeline from a plurality of display pipelines in response to at least one trigger event.

Abstract: An image forming apparatus monitors sleep-cancelling events, and when a sleep-cancelling event occurs, stores an identifier and a sleep-cancellation time of the event. If a start time of a sleep mode is reached when (i) the apparatus is in a standby mode and (ii) one or more sleep-cancelling events specifying sleep-cancellation times later than the start time have been stored, the apparatus calculates power consumption required to maintain the standby mode for a period from the start time to the earliest sleep-cancellation time, as a power-saving amount savable during the period. Also, a recovery power amount required for recovery from the sleep mode to the standby mode is calculated on the assumption that the sleep mode is started at the start time and is cancelled at the earliest sleep-cancellation time. Switching to the sleep mode is performed only when the power-saving amount is greater than the recovery power amount.

Abstract: A method and apparatus are disclosed to provide ad-hoc synchronization in industrial networks between a programmable logic controller and each I/O device without any specific protocol extensions or distributed clock scheme. An embodiment of an industrial control network comprising a Programmable Logic Controller (PLC), a network coupled to the PLC, and a plurality of networked input/output (I/O) devices coupled to the network is provided. Each I/O device comprises: inputs coupled to the network to receive data from the PLC as device input data; and outputs coupled to the network to transmit output data from the I/O device to the PLC. The embodiment further comprises a programmable timer initiating an I/O cycle for the device on a periodic basis. The I/O device is operable to determine a first time period starting at the time at which specific output data arrives from the PLC and ending when the period of the timer ends. The first time period is compared to a predetermined time period.

Abstract: A microprocessor reset control operates in one of two reset states and transitions from the first state to the second state when a first signal falls below a first threshold and from the second state to the first state when a second signal exceeds a second threshold.

Abstract: Method for controlling terminations of a media gateway, wherein a command from a media gateway controller is received containing a condition under which the command is executed. After having identified the terminations addressed by the command, it is verified whether the condition is met, and if the condition is met, the command is executed.

Abstract: A system, method, and computer program product are provided for allowing a head to enter a reduced power mode. A first processor having a first head is provided. Additionally, a second processor having a second head is provided. Furthermore, a link is provided, coupled between the first head of the first processor and the second head of the second processor for communicating first data therebetween. In operation, at least the second head of the second processor is capable of entering a reduced power mode.

Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.

Abstract: A method for managing the power of a chassis includes receiving a plurality of modular information handling systems into the chassis, receiving a plurality of information handling resources into the chassis, virtualizing access of one of the modular information handling resources to two or more of the plurality of modular information handling systems, the modular information handling systems sharing the modular information handling resource, and, upon initialization of one of the information handling systems, determining power requirements of the shared information handling resource, receiving power requirements from the information handling systems, determining whether the power requirements from the information handling system includes power requirements of the shared information handling resource, subtracting the power requirements of the shared information handling resource from the power requirements of the information handling system to determine resultant power requirements, comparing the resultant pow

Abstract: A method is provided in one example embodiment and includes receiving a first data at a first network element; determining that the first data does not match an entry in an access control list; and sending a first message to a second network element that causes the second network element to enter into a low-power state. In yet another example embodiment, the method can include receiving a second data; determining that the second data matches an entry in the access control list; buffering the second data; sending a second message to the second network element, where the second message causes the second network element to exit the low-power state; and sending the buffered second data to the second network element.

Abstract: An information processing apparatus capable of suppressing occurrence of a failure in the processing to respond to reception information received from external equipment. In a normal power mode, a CPU of a main controller executes processing to respond to incoming packets, thereby generating response packets. In a power saving mode, a microprocessor of a LAN interface executes processing to respond to incoming packets to generate response packets. During return processing for return from power saving mode to normal power mode, the LAN interface transfers an incoming packet to the main controller and to the microprocessor of the LAN interface.

Abstract: A motherboard assembly includes a motherboard and an expansion card. The motherboard includes an expansion slot with a first idle pin connected to a standby power through a resistor. The expansion card includes an edge connector having a second idle pin and first to fifth electronic switches. When the first electronic switch receives a high level signal through the first and second idle pins, the first and fourth electronic switches are turned on. The second, third, and fifth electronic switches are turned off. The second system power outputs a standby voltage through the standby voltage output terminal. When the first electronic switch receives a low level signal, the first and fourth electronic switches are turned off. The second, third, and fifth electronic switches are turned on. The standby power outputs a standby voltage through the standby voltage output terminal.

Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

Abstract: An automated programming system that includes providing a smart interface system for recognizing an intelligent module installed within the automated programming system. Configuring the intelligent module with a composite connection for transmitting information between the intelligent module and the smart interface system, and linking the intelligent module to the smart interface system for communicating information.

Abstract: Systems, apparatuses, methods, and software that implement power budget allocation optimization algorithms in multi-processor systems, such as server farms. The algorithms are derived from a queuing theoretic model that minimizes the mean response time of the system to the jobs in the workload while accounting for a variety of factors. These factors include, but are not necessarily limited to, the type of power (frequency) scaling mechanism(s) available within the processors in the system, the power-to-frequency relationship(s) of the processors for the scaling mechanism(s) available, whether or not the system is an open or closed loop system, the arrival rate of jobs incoming into the system, the number of jobs within the system, and the type of workload being processed.

Abstract: A computer system is disclosed comprising a disk drive comprising a head stack assembly (HSA), the HSA comprising a spindle motor for rotating at least one disk, and at least one head actuated over the disk. The computer system further comprises a host coupled to the disk drive, wherein the host comprises a microprocessor operable to first boot the host by reading boot data from a secondary storage device. After first booting the host, the microprocessor commands the disk drive to accumulate performance data for the HSA, and after accumulating the performance data, the microprocessor second boots the host by reading boot data from the HSA.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: There is provided a system and a method for increasing input/output (“I/O”) throughput in a data storage system. More specifically, in one embodiment, there is provided a method comprising determining an owning controller associated with each of a plurality of storage units of a storage system, receiving an I/O transaction for one of the plurality of storage units, determining if the I/O transaction is a read transaction, and selecting a path to the owning controller associated with the storage unit if the I/O transaction is a read transaction.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.