Abstract: A video apparatus includes plural interface sections such as HDMI (Registered Trademark) sections for connection with plural video signal sources, a function transferring section which transfers functions of the interface sections, and one or more function blocks for use in common to the plural interface sections. The functions are assigned to the interface sections such as HDMI sections connected with the video signal sources, via switches for example, to minimize the number of the function blocks to be provided.

Abstract: A computer program product is provided for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating at least one address control word (ACW) in the local channel memory specifying one or more host memory locations for transfer of data between the host and a control unit and including at least one ACW error checking field; generating an address control structure specifying a location in the local channel memory of a corresponding ACW and including at least one address control structure error checking field; receiving a data transfer request from the network interface that includes the addressing information; comparing the at least one ACW error checking field to the at least one address control structure error checking field; and, responsive to the fields matching, routing the data transfer request to the host memory location specified in the corresponding ACW.

Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Abstract: A notebook computer includes a keyboard, a display, a light source arranged on the keyboard or the display, and a light source control circuit. The light source control circuit includes first to third electronic switches. A control terminal of the first electronic switch is connected to a working voltage terminal. A first terminal of the first electronic switch is connected to a first terminal of the light source and a first terminal of the third electronic switch. A second terminal of the light source is connected to a standby voltage terminal. A control terminal of the second electronic switch is connected to a sleep signal terminal. A first terminal of the second electronic switch is connected to the standby voltage terminal and a control terminal of the third electronic switch. Second terminals of the first to third electronic switches are grounded.

Abstract: System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: A control device controls an external storage device with a plurality of storage units which can be driven and stopped independently. The control device comprises: a display control unit; a setting unit; and a control signal output unit. The display control unit displays on a display a selection screen that allows a user to select which storage unit from among the plurality of storage units to operate. The setting unit sets a storage unit selected by the user as an operating storage unit to be operated. The control signal output unit outputs to the external storage device a control signal for having the operating storage unit be operated.

Abstract: An integrated network chip and an electronic device using the chip are illustrated. The integrated network chip includes at least a first access interface, at least a second access interface, a power management unit (PMU) and an interface bridge. The first access interface and second access interface respectively provides the electronic device with a local area network connection function and a memory card access function. The interface bridge integrates the first access interface and second access interface by providing a hub-like functionality. The PMU provides the power and the ground to the first access interface, second access interface and the interface bridge. When the PMU detects the second access interface enters a power saving mode, the PMU provides a lower operation voltage to the second access interface.

Abstract: Techniques are provided for desktop streaming over wide area networks. In one embodiment, a computing device comprises pivot logic that is configured to be executed during a first boot of an operating system on a computing device as a pivot process that is the only process running when performing modifications to a file system on the computing device. During execution, the pivot process replaces a current set of files in the file system with a new desktop image that represents a complete view of the file system. The desktop image includes a prefetch set of files, but other files in the desktop image are represented by file metadata. The prefetch set of files includes a smallest subset of files that is needed to boot the computing device without requiring retrieval of additional files. During execution, the pivot process terminates the first boot and to invoke a second boot that is executed based on the prefetch set of files included in the new desktop image.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: A system and method for migrating domains from one physical data processing system to another are provided. With the system and method, domains may be assigned direct access to physical I/O devices but in the case of migration, the I/O devices may be converted to virtual I/O devices without service interruption. At this point, the domain may be migrated without limitation. Upon completion of the migration process, the domain may be converted back to using direct physical access, if available in the new data processing system to which the domain is migrated. Alternatively, the virtualized access to the I/O devices may continue to be used until the domain is migrated back to the original data processing system. Once migration back to the original data processing system is completed, the access may be converted back to direct access with the original physical I/O devices.

Abstract: A method for identifying the cause of degraded I/O performance between a host system and a storage controller includes initially monitoring I/O performance between the host system and the storage controller. The method further detects degraded I/O performance between the host system and the storage controller using any suitable technique. Once degraded I/O performance is detected, the method determines the cause of the degraded I/O performance by analyzing historical configuration records in the storage controller. These historical configuration records enable the storage controller to correlate the degraded I/O performance with configuration changes in the storage controller and/or the connected host systems. The method then notifies one or more host systems of the cause of the degraded I/O performance. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: Languages based in whole or in part on ideographic characters such as Chinese, Japanese, and Korean, are often are entered in a computerized text-entry system in a two-phase process. In the first phase, symbols from a first pre-conversion set are entered, then in the second phase, these pre-conversion symbols are converted into a second set of post-conversion symbols. This invention teaches a method and apparatus for the automatic conversion of pre-conversion symbols into post-conversion symbols without requiring an explicit conversion signal to be input by the user. It accomplishes this goal though the design of trigger sequences of keystrokes which are substantially functionally equivalent to an explicit conversion signal input by the user. An apparatus constructed according to the trigger sequence method is particularly well adapted for use on reduced keyboards, and in conjunction with predictive text-entry methods. Explicit constructions are shown for Chinese, Japanese, and Korean.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently.

Abstract: A method is provided for processing operation command in a computer that has a display and a host which includes a first display processing unit for local displaying and a second display processing unit for remote displaying. The operation command is from a remote data processing terminal. The method includes: receiving a first operation command from the data processing terminal, the first operation command being a power-on command; performing power-on of the computer, shielding the first display processing unit and loading only a driver of the second display processing unit according to first operation command; receiving a second operation command from the data processing terminal, the second operation command being not a power-on command; executing the second operation command to obtain operation results, the operation results being image data processed by the second display processing unit, and sending the operation results to the remote data processing terminal, for remote displaying.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: One embodiment of the present invention is an integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop. When two, four, six, or eight or more storage-shelf routers are used within a storage shelf, and the interconnections between the storage-shelf routers, disk drives, and external communications media are properly designed and configured, the resulting storage shelf constitutes a discrete, highly-available component that may be included in a disk array or in other types of electronic devices. The storage-shelf router features a disk-drive adaptation layer that allows a storage-shelf router to interface to, and manage, any of many different types of disk drives. The disk-drive adaptation layer includes a disk-profile table and associated firmware logic.