Abstract: Described embodiments provide systems and methods for balancing user sessions using load pattern forecasting are provided here. A device can determine a pattern of load distribution for a session prior to establishment of the session on a server of a computing environment. The pattern can be indicative of load on a server to run the session for a range of time. The device can determine an amount of usage of the plurality of servers on a per server basis. The usage can be indicative of sessions to be run on individual servers for the range of time. The device can select one of the plurality of servers on which to run the session based on a comparison of the pattern of load distribution for the session and the determined amounts of usage of the plurality servers. The device can assign the session to the selected server of the computing environment to balance resource usage across the computing environment.

Abstract: Some embodiments provide a method of migrating a first software defined (SD) network managed by a first network manager to a second SD network managed by a second network manager. The method of some embodiments is performed by a third network manager that provides an interface that allows a set of users to specify and review logical network components, which the first and second network managers can then respectively deploy in the first and second SD networks. The third network manager in some embodiments identifies for a migration manager a first group of two or more logical network components that the third network manager previously specified for the first network manager to deploy in the first SD network.

Abstract: An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.

Abstract: A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.

Abstract: A system is presented for provisioning resources on a target cloud platform based on a platform-independent specification of a data center. The system identifies data center entities represented within the platform-independent declarative specification and generates data structures and metadata representations of the data center entities. The system then generates instructions for provisioning services or deploying applications for creating one or more services on the target cloud platform based on the data structures and metadata representations of the data center entities according to the declarative specification. The system sends the generated instructions for execution on the target cloud computing platform, where the target cloud computing platform executes the instructions to generate the data center. The system provides users with access to the computing resources of the data center created by the cloud computing platform.

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Abstract: In one embodiment, a method includes receiving a user request to create a reminder from a client system associated with a user, wherein the user request does not specify an activation-condition for the reminder, determining one or more proactive activation-conditions for the reminder, storing the reminder in a reminder store, receiving one or more inputs associated with the user, determining a user context associated with the user based on the one or more inputs, determining the one or more proactive activation-conditions for the reminder are satisfied based on the user context, and sending instructions for presenting the reminder to the user to the client system responsive to determining the one or more proactive activation-conditions are satisfied.

Abstract: Methods and systems for implementing an abstraction layer for streaming data sources are disclosed. A request to perform an operation based on one or more keys is received using a key-value interface. A streaming data source is selected based on the request. The operation is performed using the streaming data source, wherein the operation comprises storing or retrieving one or more values based on the one or more keys.

Abstract: In a multi-source hybrid overlay network including a plurality of peers, an apparatus that recovers missing data occurring in a tree recovery process, acquires data that a peer does not have in a pull method through exchanging buffer maps with a first counterpart peer connected to a primary path recovered in the tree recovery process and at least one second counterpart peer connected to at least one candidate path, and provides data that the first counterpart peer does not have to the first counterpart peer in the push method, when a data recovery policy is a pull method, is provided.

Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: A semiconductor package includes a magnetic layer including an inner portion having a predetermined area and an outer portion disposed outward of the inner portion, a lower polymer layer disposed below the magnetic layer, and a dicing surface formed by ends of the magnetic layer and the lower polymer layer and extending along a stacked direction of the magnetic layer and the lower polymer layer. At least a part of the outer portion of the magnetic layer includes an inclined surface inclined downward in the stacked direction, and has a thickness greater than a thickness of the inner portion in the stacked direction.

Abstract: A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

Abstract: A method includes various operations and a computer program product may cause a processor to perform various operations. The operations include obtaining, for each of a plurality of baseboard management controllers (BMCs) that have been configured to form a baseboard management controller (BMC) group, an amount of load placed on the BMC, wherein a first BMC in the BMC group has been configured to operate as a BMC group leader for the BMC group. The operations further include, in response to a second BMC in the BMC group having less load than any other BMC in the BMC group, configuring the second BMC to operate as the BMC group leader and unconfiguring the first BMC to no longer operate as the BMC group leader. Still further, the operations include causing the second BMC to perform a BMC group operation operating as the BMC group leader.

Abstract: The present application provides a pixel circuit, a display panel, and a temperature compensation method for a display panel. The display panel includes a plurality of pixel units. At least one of the plurality of pixel units includes: a display layer comprising a light emitting element; and a thermoelectric conversion layer comprising a thermoelectric element having a first terminal and a second terminal, wherein the first terminal is disposed adjacent to the light emitting element and in thermal contact with the light emitting element, and the second terminal is disposed away from the light emitting element. The thermoelectric element has a first signal terminal and a second signal terminal, and is configured to generate a temperature difference voltage signal between the first signal terminal and the second signal terminal according to a temperature difference between the first terminal and the second terminal.