Abstract: A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.

Abstract: A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

Abstract: Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.

Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Abstract: A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of top-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also comprises a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality of pre-reserved blank regions are configured among the scan lines, the data lines, and the plurality of sub-pixels in the display region; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.

Abstract: Disclosed are an array substrate and a method for repairing broken lines thereof. By forming a via in an organic layer to correspond to each of the intersections between gate scan lines and source-drain data lines and depositing a second passivation layer in the via to form an aperture, a U-shaped long line can be directly laser welded to two of the apertures at two opposite sides of a broken site of one of the gate scan lines and source-drain data lines to recover connection between the two apertures of the broken line. This method saves an operation of removing an organic layer with laser and effectively reduces the machine laser loss in removing the organic layer so as to improve the repair efficiency and the repair success rate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.

Abstract: A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Abstract: A semiconductor package includes a substrate, an image sensor chip mounted on the substrate, a holder disposed on the substrate and surrounding the image sensor chip, and the holder has an inner surface facing the image sensor chip and an outer surface opposite to the inner surface. The semiconductor package further includes a transparent cover combined with the holder, and the transparent cover is spaced apart from and faces the substrate. The holder includes: a hole penetrating the holder from the inner surface to the outer surface. In addition, the semiconductor package further includes a first stopper disposed in the hole and a second stopper disposed at a position corresponding to the hole on the outer surface of the holder.

Abstract: The present invention provides an array substrate and method of repairing broken lines therefor, by forming a via on the organic layer corresponding to each intersection of the gate scan lines and the source-drain data lines, and deposing the second passivation layer in the via to form an aperture, with the vias, a U shape long line can be directly laser welded between the apertures at two ends of a broken line position to recover a connection of the broken gate scan line or the source-drain data line as the gate scan line or the source-drain data line on the substrate of the present invention is broken. The method of repairing saves the process of removing the organic layer with laser and effectively reduces the machine laser loss as removing the organic layer to raise the repair efficiency and the repair success rate. Thus, the display quality of the liquid crystal panel product is promoted.

Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device.

Abstract: A light-emitting device comprises a light-emitting semiconductor stack comprising a plurality of recesses and a mesa, each of the plurality of recesses comprising a bottom surface, and the mesa comprising an upper surface; a first electrode formed on the upper surface of the mesa; a plurality of second electrodes respectively formed on the bottom surface of the plurality of recesses; a first electrode pad formed on the light-emitting semiconductor stack and contacting with the first electrode; a second electrode pad formed on the light-emitting semiconductor stack and contacting with the plurality of second electrode; a first insulating layer comprising a plurality of passages to expose the plurality of second electrodes; and a second insulating layer comprising a plurality of spaces and formed on the first insulating layer, wherein the plurality of spaces is covered by the first electrode pad.

Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.