Abstract: A method for packaging an organic light-emitting diode (OLED) display panel includes: providing a package cover and an OLED substrate, and an OLED device arranged on OLED substrate; simultaneously printing a circle of a support and a hydrophobic barricade on an outer side of the package cover corresponding to the OLED device by means of screen printing, the support printed on an outer side of the hydrophobic barricade; and cementing the package cover and the OLED substrate. The hydrophobic barricade can effectively prevent external water vapor and oxygen from touching the OLED device. Therefore, the effect of package is enhanced, and the lifetime of the OLED device is prolonged. Further, the support and the hydrophobic barricade are formed at the same time through screen printing. Not only the method is simple but the efficiency is enhanced.

Abstract: A method for manufacturing a liquid crystal display, including: preparing a substrate on which a switching element, laminating a conductive material layer and a conductive metal layer, forming a first photosensitive film pattern on the conductive metal layer, the first photosensitive film pattern comprising a first region having a first thickness and a second region having a second thickness greater than the first thickness, forming a conductive metal pattern by etching the conductive metal layer using the first photosensitive film pattern as a mask, forming a second photosensitive film pattern that exposes a part of the conductive metal pattern by removing the first region of the first photosensitive film pattern, forming a common electrode by etching the conductive material layer by using the conductive metal pattern as a mask and forming an auxiliary electrode by etching the exposed conductive metal pattern using the second photosensitive film pattern as a mask.

Abstract: A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates. Further, the method also includes performing a post-treatment process using oxygen-contained de-ionized water on the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer; removing the dummy gates to form trenches; and forming a high-K metal gate structure in each of the trenches.

Abstract: In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other. Therefore, the present invention makes it possible to reduce snapback.

Abstract: A substrate processing apparatus includes first and second process chambers; a mounting section on which a housing vessel that houses the substrate is mounted; a vacuum transfer chamber that has a vacuum transfer machine to transfer the substrate under a negative pressure; and an atmospheric transfer chamber that has an atmospheric transfer machine that transfers the substrate under an atmospheric pressure. Timing for the atmospheric transfer chamber to take out the substrate from the housing vessel is based on a recipe remaining time, which is a remaining time of substrate processing, and an approach time, which is a time from when the substrate is taken out from the housing vessel till when the substrate is mounted to the vacuum transfer machine.

Abstract: In the GOA circuit repair method provided by the present invention, the repair signal (Repair signal) is received by the GOA unit circuits of the Nth stage and the N+1th stage via the repair signal line (L1) respectively to be the output signal of the GOA unit circuit of the Nth stage, and the scan control signal of the GOA unit circuit of the N+1th stage to achieve the repair to the GOA unit circuit of the Nth stage; or the start signal (STV) is received by the GOA unit circuits of the N+1th stage and the N+2th stage via the start signal line (L5) respectively to be the output signal of the GOA unit circuit of the N+1th stage, and the scan control signal of the GOA unit circuit of the N+2th stage to achieve the repair to the GOA unit circuit of the N+1th stage, and meanwhile, the repair signal (Repair signal) is received by the GOA unit circuits of the N+2th stage and the N+3th stage via the repair signal line (L1) respectively to be the output signal of the GOA unit circuit of the N+2th stage, and the scan

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract: According to an embodiment, a semiconductor memory device comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a first layer. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end connected to the substrate and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The first layer is surrounded by the stacked body in a plane parallel to the substrate. Moreover, a width in a first direction parallel to the substrate, of the first layer is larger than a width in the first direction of the semiconductor layer.

Abstract: A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: A device includes a transition metal dichalcogenide layer having a first edge with a zigzag atomic configuration. A metallic material has a portion overlapping the transition metal dichalcogenide layer. The metallic material has a second edge contacting the first edge of the transition metal dichalcogenide layer.

Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

Abstract: In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement.

Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

Abstract: Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.

Abstract: A method of forming a conductive portion in an insulating material. The insulating material includes carbon and at least one other constituent. The method includes exposing the insulating material to ions to preferentially remove the other constituent.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: A semiconductor device includes a semiconductor element, a connection electrode formed on the semiconductor element, and alignment marks formed on the semiconductor element. At least one of the alignment marks is made of a magnetic material.

Abstract: The semiconductor optical device has a chip of semiconductor lamination having a first semiconductor layer of a first conductivity type having a first surface, a second semiconductor layer of a second conductivity type opposite to the first conductivity type having a second surface, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, the chip having side surface including a first side surface which is contiguous to the second surface, forms an obtuse angle with the second surface, extends across the second semiconductor layer and the active layer, and enters the first semiconductor layer, and a cracked surface which is contiguous to the first side surface, a first conductivity type side electrode formed on the first surface, and a second conductivity type side electrode formed on the second surface, wherein in-plane size of the semiconductor lamination is 50 ?m or less.

Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.