Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.

Abstract: Embodiments are directed to a method of programming a semiconductor memory device, the memory device including: a plurality of memory cell transistors arranged in a plurality of transistor strings; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the transistor strings; and a plurality of bit lines, each bit line connected to at least one of the transistor strings, the method comprising: applying a first voltage, and then applying a programming voltage to a selected word line corresponding to the selected memory cell transistor; and in advance of applying the first voltage to the selected word line, applying a second voltage to at least one neighboring word line that neighbors the selected word line, the neighboring word line connected to a neighboring, unselected memory cell transistor of the selected transistor string, to ensure precharging of a channel region of another, unselected transistor string between a first, unselected transistor of the unsele

Abstract: A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage.

Abstract: A method of programming a nonvolatile memory device is provided. The method includes providing a plurality of memory cells coupled to a wordline, the plurality of memory cells grouped into a plurality of groups, each group including at least two memory cells, such that for each cell of the plurality of memory cells that has memory cells adjacent both sides, the memory cells immediately adjacent either side of the cell belong to different groups from each other. The method further includes selecting one group from the plurality of groups, and performing a program operation including applying a program pulse to the selected group while one or more non-selected groups of the plurality of groups are inhibited from being programmed.

Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

Abstract: Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

Abstract: A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.

Abstract: A system including a programming module and an interference module. The programming module is configured to determine a programming value to which a state of a target cell is to be programmed, wherein the programming value is determined based on states of one or more cells near the target cell. The interference module is configured to generate interference values based on (i) the state of the target cell and (ii) the states of the one or more cells near the target cell. The programming module is further configured to determine the programming value based on at least one of the interference values selected according to (i) the state of the target cell and (ii) the states of the one or more cells near the target cell.

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.

Abstract: A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

Abstract: A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.

Abstract: According to example embodiments, a solid state drive system includes at least one semiconductor memory, a control circuit including first connection terminals, and second connection terminals. The first connection terminals may be configured to supply one or more operational voltages to the at least one semiconductor memory. The second connection terminals may be configured to supply one or more test voltages to the at least one semiconductor memory.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.

Abstract: An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.

Abstract: A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.