Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between conductive features. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate; a bit line structure disposed over and electrically connected to the first source/drain region; a capacitor contact disposed over and electrically connected to the second source/drain region; a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure comprises an air gap; and a second spacer structure disposed over the first spacer structure, wherein the air gap is covered by the second spacer structure.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. The isolation structure includes a curved bottom surface.

Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.

Abstract: A through electrode substrate includes a substrate provided with a through hole; a through electrode having a sidewall portion extending along a sidewall of the through hole, and a first portion positioned on a first surface of the substrate and connected to the sidewall portion; an inorganic film that at least partially covers the first portion of the through electrode from the first side and is provided with an opening positioned on the first portion; and a first wiring structure including at least a first wiring layer having an insulation layer that is positioned to the first side of the inorganic film and includes at least an organic layer provided with an opening communicating with the opening of the inorganic film, and an electroconductive layer connected to the first portion of the through electrode through the opening of the inorganic film and the opening of the insulation layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Abstract: A method includes forming a body region of a first conductivity type and a doped region of a second conductivity type in a semiconductor substrate; forming a gate structure the substrate, and first gate spacers respectively on first and second sides of the gate structure; depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers respectively on the first and second sides of the gate structure; removing a first one of the third gate spacers from the first side of the gate structure, while leaving a second one of the third gate spacers on the second side of the gate structure; and patterning the second spacer layer into a second gate spacer by using the second one of the third gate spacers as an etching mask.