Patents Examined by Theresa T. Doan
  • Epitaxy regions with large landing areas for contact plugs
    Patent number: 11652105
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
  • Semiconductor device and manufacture thereof
    Patent number: 11646314
    Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Meng-Hung Shen, Jiann-Tyng Tzeng
  • Interconnect structures for semiconductor devices and methods of manufacturing the same
    Patent number: 11626326
    Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
  • Fin Field-Effect Transistor and method of forming the same
    Patent number: 11626510
    Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang, Tzu-Chung Wang, Shu-Yuan Ku
  • Semiconductor device and method of fabricating the same
    Patent number: 11616059
    Abstract: A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Sung Woo
  • Epitaxy regions extending below STI regions and profiles thereof
    Patent number: 11610890
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, forming a plurality of semiconductor fins protruding higher than top surfaces of the isolation regions, forming a gate stack on the plurality of semiconductor fins, forming a gate spacer on a sidewall of the gate stack, and recessing the plurality of semiconductor fins to form a plurality of recesses on a side of the gate stack. The plurality of recesses extend to a level lower than top surfaces of the isolation regions. Epitaxy processes are performed to grow an epitaxy region, wherein the epitaxy region fills the plurality of recesses.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shahaji B. More
  • Power semiconductor module and method for fabricating the same
    Patent number: 11610830
    Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies AG
    Inventors: Christian Schweikert, Juergen Hoegerl, Olaf Hohlfeld, Waldemar Jakobi
  • Method of fabricating semiconductor device
    Patent number: 11610836
    Abstract: A method for fabricating a semiconductor device is provided and includes the following steps: providing a substrate; forming a lower electrode on the substrate; forming at least one sub-dielectric layer on the lower electrode; patterning the dielectric layer to form an intermediate dielectric layer, where the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; forming a hole by etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer; filling at least one plug into the hole; and forming an upper electrode on the intermediate dielectric layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 21, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chi-Hua Yu, Shih-Tsung Kung, Wen-Chun Chung, Yi-Hong Hong
  • Semiconductor device and method of forming same
    Patent number: 11605635
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Semiconductor structure and method for forming the same
    Patent number: 11605726
    Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 14, 2023
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Hansu Oh, Pengchong Li, Xuejie Shi, Yiyu Chen, Bo Su
  • Transistor and method for manufacturing the same
    Patent number: 11594645
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Treatment for adhesion improvement
    Patent number: 11594410
    Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yi Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Semiconductor structure and method of forming semiconductor package
    Patent number: 11587863
    Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Kuang Kao, Ta-Chih Peng, Ming-Hong Kao, Huei-Wen Yang
  • Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances
    Patent number: 11587862
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 21, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner
  • Thermal bump networks for integrated circuit device assemblies
    Patent number: 11587843
    Abstract: Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Prasad Ramanathan, Nicholas Neal, Chandra Mohan Jha
  • Semiconductor memory device and method of forming the same
    Patent number: 11587933
    Abstract: An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Toshiyasu Fujimoto, Hiromitsu Oshima
  • Electronic IC device comprising integrated optical and electronic circuit component and fabrication method
    Patent number: 11581249
    Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Pierre Carrere, Francois Guyader
  • High voltage field effect transistors with self-aligned silicide contacts and methods for making the same
    Patent number: 11575015
    Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 7, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuhiro Togo, Jun Akaiwa, Hiroshi Nakatsuji, Masashi Ishida
  • Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices
    Patent number: 11575028
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • Frame-array interconnects for integrated-circuit packages
    Patent number: 11562954
    Abstract: Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong