Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

Abstract: A capacitor structure for an integrated circuit (IC) is provided. The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal layer is positioned over and between the metal pillars. At least one contact is operatively coupled to a first metal pillar of the plurality of metal pillars. The metal-insulator-metal layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the metal-insulator-metal layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.

Abstract: Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: The present disclosure provides an OLED device, including a substrate, a light-emitting unit arranged on the substrate, and an encapsulation structure arranged on a surface of the light-emitting unit distal to the substrate, the encapsulation structure includes a deoxygenation layer made of an active metal, used to react with oxygen, the active metal is a metal with an activity of reacting with oxygen being between those of aluminum and copper.

Abstract: A packaging method and a packaging structure are provided. The packaging method includes providing a cap wafer including a groove; forming a sacrificial layer in the groove and a first device on the sacrificial layer; providing a substrate wafer and a second device formed on the substrate wafer; bonding a surface of the cap wafer having the first device formed thereon with a surface of the substrate wafer having the second device formed thereon, to form an electrical connection between the first device and the second device; and removing the sacrificial layer from a side of the cap wafer away from the substrate wafer, to form a cavity. The first device is located in the cavity.

Abstract: A MEMS vibration element includes: a base unit; a fixed unit fixed to the base unit; a movable unit that is movable relative to the fixed unit; and an elastic support unit that elastically supports the movable unit at the base unit. The elastic support unit is made of a material different from a material of the fixed unit and the movable unit.

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Abstract: The disclosure relates to an OLED display substrate, a manufacturing method and a display apparatus. The OLED display substrate comprises a base substrate, and a plurality of light-emitting elements and a plurality of pixel defining layers formed on the base substrate, wherein a pixel defining layer is located between any two adjacent light-emitting elements of the plurality of light-emitting elements; and a surface of the pixel defining layer facing away from the base substrate comprises an accommodating portion, a bottom surface of the accommodating portion and the surface of the pixel defining layer facing away from the base substrate are located at different planes, and an orthographic projection of the accommodating portion on the base substrate does not overlap with an orthographic projection of the plurality of light-emitting elements on the base substrate. The method for manufacturing the OLED display substrate is configured to manufacture the above OLED display substrate.

Abstract: A first electrode (110) has optical transparency, and a second electrode (130) has light reflectivity. An organic layer (120) is located between the first electrode (110) and the second electrode (130). Light-transmitting regions (a second region (104) and a third region (106)) are located between a plurality of light-emitting units (140). An insulating film (150) defines the light-emitting units (140) and includes tapers (152, 154). A sealing member (170) covers the light-emitting units (140) and the insulating film (150). A low reflection film (190) is located on the side opposite to a substrate (100) with the second electrode (130) therebetween. The low reflection film (190) covers at least one portion of the tapers (152 and 154).

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED packages are disclosed. A light-altering material may be provided in particular configurations within an LED package to redirect light toward a primary emission direction. The light-altering material may be arranged on any of a first face, a second face, or a plurality of sidewalls of an LED chip in the LED package. In certain embodiments, a lumiphoric material may be arranged on one or more of the sidewalls. A superstrate may be arranged to mechanically support the LED chip from the first face. The light-altering material may be arranged on or dispersed within the superstrate. In certain embodiments, the primary emission direction of the LED package is substantially parallel to the second face of the LED chip in the LED package. An overall thickness or height of the LED package may be less than or equal to 0.25 mm.

Abstract: A semiconductor device is disclosed, which comprises a capacitor structure formed over a device region of a substrate, and a buffer layer. The capacitor structure comprises a lower electrode having a U-shaped profile that opens away from the substrate, the U-shaped profile defines an interior surface and an opposing exterior surface; a dielectric liner extending into the U-shaped profile and conformally covering the interior surface of the lower electrode; and an upper electrode formed over the dielectric liner, extending into and filling the U-shaped profile, the upper electrode) includes a top conductive layer. The buffer layer formed on the top conductive layer of the upper electrode, wherein the lattice constant of the buffer layer is greater than that of the top conductive layer.

Abstract: Provided is a spin-orbit-torque magnetization rotational element that suppresses re-adhesion of impurities during preparation and allows a write current to easily flow. The spin-orbit-torque magnetization rotational element includes a spin-orbit torque wiring that extends in a first direction, and a first ferromagnetic layer that is located on a side of one surface of the spin-orbit torque wiring. A side surface of the spin-orbit torque wiring and a side surface of the first ferromagnetic layer form a continuous inclined surface in any side surface.

Abstract: A semiconductor device includes a P-type substrate, a P-type well region, an N-type well region, an N-type guard ring region, an insulating layer, a poly gate disposed, and a bulk region. The P-type well region is disposed on the P-type substrate and includes source regions and drain regions each spaced apart from the other. The N-type well region disposed and spaced apart from the P-type well region on the P-type substrate. The N-type guard ring region is disposed around perimeters of the P-type well region and the N-type well region. The insulating layer is disposed around the P-type well region and the N-type well region on the N-type guard ring region. The poly gate is disposed around the perimeter of the P-type well region and the N-type well region, respectively, on the insulating layer. The bulk region is disposed on the N-type guard ring region adjacent the poly gate.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: In a method of manufacturing a semiconductor device, the method includes: forming a stack structure; forming a channel layer penetrating the stack structure; forming a first dielectric layer in the channel layer; forming a second dielectric layer in the first dielectric layer; forming an opening by selectively etching the first dielectric layer; selectively etching the second dielectric layer exposed through the opening; and forming a pad in the opening.

Abstract: A display device includes a display module, a window disposed above the display module, an optical film disposed between the display module and the window, an adhesive layer, and a refractive index matching pattern. The window includes a base substrate and a bezel pattern overlapping with the base substrate and defining a first transmissive area and a second transmissive area isolated from the first transmissive area in a plane view. The optical film includes a first open area defined therein to correspond to the second transmissive area. The adhesive layer couples the window with the optical film. The refractive index matching pattern is disposed in the first open area and has a refractive index of about 90% to about 110% of the adhesive layer. The first open area is defined as an area in which the optical film is not disposed.

Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.

Abstract: A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1?L2 are satisfied.

Abstract: A display device is provided, including: a display panel including a display face and a first face opposite to the display face; an optical module configured to converge light transmitted through the display panel, the optical module being located on a side of the first face facing away from the display face; and a camera configured to receive light converged by the optical module, the camera located on a side of the optical module facing away from the first face and spaced apart from the optical module, the camera including a light incident face onto which light is incident. A projection of the optical module in a direction perpendicular to the first face of the display panel falls into display area of the display panel, and an area of the projection of the optical module is larger than an area of the light incident face of the camera.