Abstract: Systems and methods are presented for receiving, at a server computer associated with an industrial asset cloud computing system, a command representing an event, from a mobile device of a plurality of mobile devices, the command comprising instructions for changing a data object in a data domain, determining, a command processor responsible for processing the command, and routing the command to the command processor responsible for processing the command, wherein the command processor accesses the data domain associated with the command to change the data object in the data domain according to the instructions of the command. Systems and methods are further presented for detecting, by the server computer, a state change in the data domain indicating that the data object has been changed, and preparing the changed data object to be consumed by mobile devices operated by users authorized to access the data object.

Abstract: A cationic nanoparticulate material comprises polymer and a BF4?, PF6? or SbF5? counterion. A layer of an organic electronic device, such as an organic light-emitting device, comprises the nanoparticulate material dispersed in an organic semiconducting layer.

Abstract: A method of manufacturing an optoelectronic device, comprising the successive steps of: a) providing a substrate at least partially made of a semiconductor material and having first and second opposite faces; b) forming light-emitting diodes on the substrate, each light-emitting diode comprising a semiconductor microwire or nanowire covered by a shell; c) forming an encapsulation layer surrounding the light-emitting diodes; d) forming conductive pads on the encapsulation layer, on the side of the encapsulation layer opposite to the substrate, in contact with the light-emitting diodes; and e) forming through openings in the substrate from the side of the second face, said openings being opposite at least part of the light-emitting diodes and delimiting walls in the substrate.

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

Abstract: A semiconductor device including a semiconductor substrate; a conductive film covering a front face of the semiconductor substrate, a front face of the conductive film having plural straight-line shaped concave portions disposed in parallel to each other; and a protecting film covering the front face of the conductive film, the protecting film having an opening that has an edge forming an angle with the plural concave portions of greater than 0° and less than 90°, and that partially exposes the conductive film.

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

Abstract: The present disclosure provides an array substrate and a liquid crystal display panel. The array substrate, including a display area and a non-display area, comprises: a substrate; a patterned first metal layer disposed on the substrate, wherein the first metal layer in the non-display area includes at least two first metal lines; an insulating layer disposed on the first metal layer; and a patterned second metal layer disposed on the insulating layer, wherein the second metal layer in the non-display area includes at least two second metal lines; wherein the first metal lines and the second metal lines surround the display area and connect to each other through a through-hole in the insulating layer, and at least one of the first metal lines or the second metal lines electrically connects to a ground line of the array substrate.

Abstract: An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of ˜105, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.

Abstract: A thin film transistor includes an oxide semiconductor layer on a substrate. The oxide semiconductor layer includes a channel portion, a first channel connecting portion connected to a first end of the channel portion, and a second channel connecting portion connected to a second end of the channel portion. A thickness of the second channel connecting portion is different from a thickness of the first channel connecting portion. The first end of the channel portion has a same thickness as the thickness of the first channel connecting portion, and the second end of the channel portion has a same thickness as the thickness of the second channel connecting portion.

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: A display panel and a display device are provided. The display panel includes a display area configured to display an image and a dummy pixel area disposed outside of the display area. The dummy pixel area has a plurality of dummy pixels disposed therein. Each dummy pixel includes a pixel protection unit. The dummy pixels are defined by crisscrossing data metal lines and gate metal lines in a vertical direction and a horizontal direction, respectively. A pattern of a projection of a semiconductor layer on the horizontal plane intersects the corresponding data metal line, is separated from the corresponding gate metal line, and is disposed toward a center of each dummy pixel, to prevent the display device from poor display due to contact between the semiconductor layer and the gate metal lines in the dummy pixel area when electrostatic discharge occurs.

Abstract: A technique related to a bonded semiconductor substrate capable of reducing an interface resistance is provided. The semiconductor substrate comprises a single-crystalline SiC substrate and a polycrystalline SiC substrate. The single-crystalline SIC substrate and the polycrystalline SiC substrate are bonded. A bonded region of the single-crystalline SiC substrate and the polycrystalline SiC substrate contains 1×1021 (atoms/cm3) or more of particular atoms.

Abstract: An electroluminescence display device, including a first electrode and a second electrode facing each other; a quantum dot emission layer disposed between the first electrode and the second electrode, the quantum dot emission layer including a plurality of quantum dots and not including cadmium, wherein the quantum dot emission layer includes a red emission layer disposed in a red pixel, a green emission layer disposed in a green pixel, and a blue emission layer disposed in a blue pixel, wherein the device has color reproducibility according to a DCI standard of greater than or equal to about 89%.

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED packages are disclosed. A light-altering material may be provided in particular configurations within an LED package to redirect light toward a primary emission direction. The light-altering material may be arranged on any of a first face, a second face, or a plurality of sidewalls of an LED chip in the LED package. In certain embodiments, a lumiphoric material may be arranged on one or more of the sidewalls. A superstrate may be arranged to mechanically support the LED chip from the first face. The light-altering material may be arranged on or dispersed within the superstrate. In certain embodiments, the primary emission direction of the LED package is substantially parallel to the second face of the LED chip in the LED package. An overall thickness or height of the LED package may be less than or equal to 0.25 mm.

Abstract: Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.

Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.

Abstract: Provided is a spin-orbit-torque magnetization rotational element that suppresses re-adhesion of impurities during preparation and allows a write current to easily flow. The spin-orbit-torque magnetization rotational element includes a spin-orbit torque wiring that extends in a first direction, and a first ferromagnetic layer that is located on a side of one surface of the spin-orbit torque wiring. A side surface of the spin-orbit torque wiring and a side surface of the first ferromagnetic layer form a continuous inclined surface in any side surface.

Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.