Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A method for manufacturing a semiconductor device that mix mounts non-volatile memories and analog IC's may include the steps of: (a) forming a gate insulation layer 20, a floating gate 22, and a selective oxide insulation layer 24 on a semiconductor substrate 10; (b) forming an insulation layer 12 and a lower electrode 32 that composes a capacitor 300; (d) forming, in a capacitor region 3000, an insulation layer 31 by thermally oxidizing an upper surface section of the lower electrode 32; and (f) forming an intermediate insulation layer 26 and a control gate 23 that form a memory transistor 200, and a dielectric layer 30 and an upper electrode 34 that form the capacitor 300.

Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

Abstract: The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal structure and a second exposed metal structure. The metal feature is selectively formed on the first exposed metal structure without forming on the second exposed metal structure. By adjusting a concentration of stabilizer in an electroless plating solution, the metal feature is electrolessly plated on the first exposed metal structure without plating metal on the second exposed metal structure.

Abstract: A semiconductor device has a field-effect transistor with a source, drain, and channel formed in an active region surrounded by a field region. The boundary between the channel region and field region includes crenellations that reduce the effect of contaminating particles and defects. The crenellated boundary can be formed by polysilicon-buffered local oxidation of silicon, or by use of a crenellated mask pattern.

Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.

Abstract: A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second impurity diffusion regions of a second conductivity type on both sides of the gate electrode. A high leak current structure is formed which makes a leak current density when a reverse bias voltage is applied across the first impurity diffusion region and first well become higher than a leak current density when the same reverse bias voltage is applied across the second impurity diffusion region and first well.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Abstract: A first insulating film is formed on a semiconductor substrate. A first pattern group having a plurality of first conductors respectively having a first width and separated from each other by a first interval is formed on the first insulting film. A second conductor having a second width larger than the first width is formed separately from a first conductor of the plurality of first conductors at an end of the first pattern group by a first distance in parallel with the plurality of first conductors. A third conductor having a width equal to the second width is formed on the same side as the second conductor with respect to the first pattern group and separated from the first conductor by the first distance. A fourth conductor having a width equal to the second width is formed between the second and third conductors and separated from the first conductor by the first distance.

Abstract: A ferroelectric thin-film element has a Si substrate and a thin-film laminate formed on the Si substrate, the thin-film laminate being a buffer layer epitaxially grown on the Si substrate, a metallic thin film lower electrode epitaxially grown on the buffer layer, a ferroelectric thin film orientationally grown or epitaxially grown on the lower electrode, and an upper electrode formed on the ferroelectric thin film. A portion of the thin-film laminate may be supported by air.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract: The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.

Abstract: A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after performing a thermal process on a refractory metal silicide layer, thereby having a stable operation characteristic, and a method for manufacturing the same are provided.

Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.

Abstract: A wafer pair comprising a substantially defect-free germanium wafer and methods of making the same. The wafer pair comprises the substantially defect-free germanium wafer directly bonded to a silicon wafer. The method of making the wafer pair comprises placing the silicon wafer in a wafer-bonding chamber, placing the germanium wafer on top or on bottom of the silicon wafer, and applying a local force to either the germanium wafer or to the silicon wafer to initiate bonding of the germanium wafer to the silicon wafer. The bonding occurs under a temperature ranging from about 23° C. to about 600° C. and under a vacuum condition inside a wafer-bonding chamber.

Abstract: Low-k dieclectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.

Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.

Abstract: An extended drain metal oxide semiconductor field effect transistor (EDMOSFET) with a source field plate is provided.