Abstract: A cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged symmetrically on portions of the first and second active areas. A first signal line extends between drain areas of the first transistor and the gate area of the second transistor. A second signal line extends between drain areas of the second transistor and the gate area of the first transistor. Metal lines can be provided to connect a source voltage, data signal lines, or control signals to common source areas of the first and second transistors. Methods for constructing cross-coupled transistor pairs are also provided.

Abstract: A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with a single common layer of conductive polysilicon which extends into each trench and overlies the silicon surface which connects adjacent trenches. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The trench is from 0.2 to 0.25 microns deeper than the channel region. The device has a very low figure of merit and is useful especially in low voltage circuits.

Abstract: The present invention provides a semiconductor memory device in which a first insulation film and a second insulation film are laminated on a source and a drain of an access transistor to form a laminated insulation film, wherein the first insulation film is the same as an insulation film used as a sidewall for a logic transistor, and the second insulation film is the same as an encircling insulation film encircling the sidewall. Furthermore, the top surface of the laminated insulation film is positioned at substantially the same height as that of a silicide film on a gate electrode of the access transistor. On the other hand, a method for fabricating a semiconductor memory device according to the present invention polishes a logic region and a memory cell region together so as to expose gate electrodes of a logic transistor and an access transistor, and further polishes a laminated insulation film on a source and a drain of the access transistor.

Abstract: A method for making a metal-insulator-semiconductor field effect transistor (MISFET) having an oxidized aluminum nitride gate insulator formed on a silicon or gallium nitride substrate. The method of making the MISFET comprises the steps of depositing an aluminum nitride layer on the entire upper surface of the silicon or gallium nitride substrate. Subsequently, the aluminum nitride layer is oxidized to convert it into an oxidized aluminum nitride layer which acts as a gate insulator of the MISFET. Portions of the oxidized aluminum nitride layer are etched to form a plurality of openings that expose regions to become the source and drain regions of the substrate. The source and drain regions are formed in the plurality of openings by conventional techniques including diffusion and ion-implantation. Finally, a metal layer is formed in the plurality of openings of the oxidized aluminum nitride layer, wherein the metal layer contacts the source and drain regions of the substrate.

Abstract: A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon oxide is deposited on the first insulating film. The deposition condition of the second insulating film is varied during the deposition so that the etching rate of the second insulating film increases from a lower portion toward an upper portion. Thereby, a contact hole which is formed by etching through the first and second insulating films has a tapered configuration to improve a reliability of a connection made therein.

Abstract: A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.

Abstract: A method for growing strain-engineered, self-assembled, semiconductor quantum dots (QDs) into ordered lattices. The nucleation and positioning of QDs into lattices is achieved using a periodic sub-surface lattice built-up on a substrate, stressor layer, and spacer layer. The unit cell dimensions, orientation and the number of QDs in the basis are tunable. Moreover, a 2D lattice can be replicated at periodic intervals along the growth direction to form a three-dimensional (3D) lattice of QDs.

Abstract: Within a stacked gate field effect transistor (FET) device, as well as a method for fabrication thereof and a method for operation thereof, there is provided a stacked gate field effect transistor (FET) device comprising a layered stack of a tunneling dielectric layer, a floating gate electrode, an inter-gate electrode dielectric layer and a control gate electrode formed upon a semiconductor substrate. To enhance performance of the stacked gate field effect transistor (FET) device, at least one of: (1) the floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) a pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.

Abstract: A semiconductor display device which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask. and thus impurity concentrations of the Lov regions and the Loffregions can be independently controlled.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircular or semi-elliptic. The stress applied to the conductive layer having the grooves is divided into a vertical component and a horizontal component with respect to the surface of the conductive layer. Accordingly, the stress applied vertically to the conductive layer is reduced, making it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to material layers under the conductive layer.

Abstract: A method and a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. On the substrate, the circuit layout comprises a plurality of strips of first circuit structure and at least two strips of second circuit structure located on the substrate. Each of the strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure for the purpose of averaging polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during the chemical mechanical polishing process for reducing defects.

Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.

Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.