Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Abstract: Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.

Abstract: Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.

Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.

Abstract: The present invention provides a readout integrated circuit and an operation method thereof. The readout integrated circuit includes a readout circuit, a line buffer and a communication interface circuit. The readout circuit reads out a plurality of row sensing results of a plurality of sensor rows of a sensor. The line buffer is coupled to the readout circuit for temporarily storing a current row sensing result of a current sensor row of the sensor. The communication interface circuit is coupled to the line buffer. After the current row sensing result of the current sensor row is temporarily stored into the line buffer, the communication interface circuit outputs the current row sensing result in real time to a host circuit.

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).

Abstract: An integrated circuit device that has improved write margin at low operating voltages is disclosed. The integrated circuit device can include an SRAM array that has end power select circuits that can include selection circuits that provide a controllable impedance path between a power supply potential and an array power line. A power supply detection circuit may provide an assist enable signal when a power supply potential is low enough that write assist is needed. A power control circuit may provide end power control signals to end power select circuits to selectively control an impedance path between a power supply potential and an array power line to provide an I-R drop to a selected memory cell. In this way, write margins may be improved at low operating voltages.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.

Abstract: Disclosed are various embodiments of memristive devices comprising a number of nodes. Memristive fibers are used to form conductive and memristive paths in the devices. Each memristive fiber may couple one or more nodes to one or more other nodes. In one case, a memristive device includes a first node, a second node, and a memristive fiber. The memristive fiber includes a conductive core and a memristive shell surrounding at least a portion of the conductive core along at least a portion of the memristive fiber. The memristive fiber couples the first node to the second node through a portion of the memristive shell and at least a portion of the conductive core.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.

Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.

Abstract: The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage config