Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.

Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.

Abstract: Disclosed herein is a furniture having a wireless charging function, including: one or more transmission coil units disposed on the same plane of a flat plate of the furniture; and a central transmission controlling unit configured to select at least one transmission coil unit corresponding to a wireless power reception apparatus when the wireless power reception apparatus is placed on the flat plate, and to transmit a wireless power signal through the selected transmission coil unit, the central transmission controlling unit being installed separately from the plurality of transmission coil units.

Abstract: A method for designing an integrated circuit. The method may include obtaining a register-transfer level (RTL) file for the integrated circuit. The RTL file may include hardware description language code that describes various modules for the integrated circuit. The method may further include selecting, within the RTL file, various state elements having a predetermined clock skew. The method may further include associating, in response to selecting the state elements, the state elements with a predetermined clock header. The method may further include generating a gate-level netlist using the RTL file. The state elements may be assigned to the predetermined clock header in the gate-level netlist. The method may further include generating, using the gate-level netlist, a clock network for the integrated circuit. The state elements in the clock network may have the predetermined clock skew.

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.

Abstract: A non-transitory computer-readable recording medium stores a state machine dividing program that causes a computer to execute a process including: determining whether a design value based on circuit information that indicates a circuit that controls a computation process by using a state machine is greater than a predetermined reference value; and dividing, when the design value is greater than the reference value, the state machine into a plurality of state machines.

Abstract: Disclosed is a battery management system for transmitting a secondary protection signal and a diagnosis signal using a small number of insulation elements. N battery management units included in the battery management system transmit at least two pieces of data via one communication line through time division. N data signals transmitted from the N battery management units are transmitted in a sequential order or are mixed to one signal and transmitted to an external device.

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection.

Abstract: A power storage system mounted on a vehicle including: a power storage device (10) that performs charging and discharging; a voltage monitoring unit (20) that detects a voltage of the power storage device (10); and a controller (50) that controls charging and discharging of the power storage device (10), wherein the controller (50) performs consistency determination processing, which determines whether the controller (50) and the voltage monitoring unit (20) are consistent, based on control information that is predefined for the power storage device (10) for which the controller (50) controls charging and discharging and, if it is determined in the consistency determination processing that the controller (50) and the voltage monitoring unit (20) are not consistent, performs control so that the power storage device (10) does not perform charging and discharging.

Abstract: A computer system with one or more processors and memory performs a breadth-first-search for an analysis of a digital circuit that includes a plurality of components. The computer system identifies two or more N generation components, initiates processing of the two or more N generation components, and subsequent to initiating the processing of the two or more N generation components, receives results of processing a subset, less than all, of the two or more N generation components. Prior to receiving results of processing all of the N generation components, the computer system identifies one or more N+1 generation components, and initiates processing of the one or more identified N+1 generation components. Subsequently, the computer system receives results of processing at least a subset of the one or more identified N+1 generation components.

Abstract: An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘C’.

Abstract: A method for parasitic capacitance extraction for integrated circuit (IC) designs fabricated involving multiple patterning that includes identifying, at a computing system, metal features in a metal layer of an IC design and generating, at the computing system, a graph based on spacing relationships between the metal features. The method further includes predicting, at the computing system, which metal features are to be formed by the same mask in the multiple patterning lithography process from the graph. The method further can include performing, at the computing system, a parasitic capacitance extraction analysis of the IC design utilizing the prediction of which metal features are to be formed by the same mask, and performing, at the computing system, timing analysis on the IC design utilizing the list of vertices sharing the same designators and the parasitic capacitance extraction calculations.

Abstract: A method for reconstituting a diagram of an electrical installation including a plurality of electrical elements connected to a power source via protective elements arranged in an electrical panel. The wired electrical elements of the installation are identified using the electrical panel. The tree structure of the electrical connections of the elements identified and the position of each element in the arborescence are automatically determined. An electrical diagram of the installation is deduced using the tree structure of the electrical connections and the position of each element in the arborescence.

Abstract: This disclosure provides systems, methods and apparatus for charging pads for use with wireless power systems. In one aspect a vehicle charging pad having a reduced thickness is provided. A charging pad may include multiple wire coils and a ferrite block backing. By forming a longitudinally extending slot in the ferrite block, a portion of the wires extending from the coils can be routed through the slot in the ferrite block to decrease the overall thickness of the charging pad.

Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.

Abstract: Described is an energy share pack comprising a housing, at least one energy storage component within the housing, at least one energy conversion component within the housing, and a connection point for connecting to more than one of energy users, energy sources and other energy share packs simultaneously for sharing energy. The energy share pack may have an energy generation component for generating harvestable energy, and two or more ports of any combination of the following types: bidirectional power port, bidirectional USB port, unidirectional output power port, and unidirectional input power port. The share pack ports may operate simultaneously at different voltage levels, and at least one port may be bi-directional. Furthermore, the share packs may have an integrated display for providing information on the energy share pack in which the display is integrated and information about other energy share packs connected thereto.

Abstract: A solar cell phone includes a housing having a keypad, a display screen, other electronic components and a rechargeable battery. A diode switch within the housing is electrically connected to the rechargeable battery. A plurality of solar panels are mounted to the housing and electrically connected to the diode switch. The diode switch will allow the solar panels to supply electrical power to the rechargeable battery. An auxiliary battery within the housing receives electrical power from the solar panels. The auxiliary battery will store the electrical power to recharge the rechargeable battery when the diode switch is in a non-operative position, so that the rechargeable battery will continue to operate the keypad, the display screen and the other electronic components within the housing.

Abstract: Implementations of the present disclosure involve methods and systems for modeling input capacitance for a component of an electronic circuit design to accurately and quickly analyze the performance of the circuit. In particular, the methods and systems may provide for an estimated input capacitance for one or more transistor components of the circuit. To determine the estimated input capacitance of a transistor, a computing system may obtain technical information about the circuit and determine one or more virtual nets that include connections between the adjusted transistor and other transistors (or other components) of the circuit design. This information may be utilized by the computing system to calculate an estimated input capacitance for the adjusted transistor of the circuit design. The calculated input capacitance of the transistor may be added into a simple simulation of the circuit design to obtain one or more operational parameters or circuit performance characteristics.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.