Abstract: The present invention includes a cellular pilot signal detector or searcher for use in a cellular mobile communications unit. The signal detector uses a matched filter to detect a pilot signal transmitted from a cellular base station. The matched filter includes a plurality of taps and a plurality of delays located between adjacent taps. The signal components of a received digital signal are held on the taps of the matched filter by the delays. The matched filter compares the signal components of the received signal to an expected or searched for digital pattern. The matched filter puts out a relatively large signal if the received digital signal matches the expected digital pattern. The matched filter can also be used in parallel with a correlator.

Abstract: Block-encoded transmissions of a multi-antenna terminal unit are effectively detected in the presence of co-channel interfering transmissions when the base station has a plurality of antennas, and interference cancellation is combined with maximum likelihood decoding. More specifically, the signals received at the base station antennas are combined in a linear combination that relates to the channel coefficients between the various transmitting terminal units and the base antennas. By selecting proper coefficients for the linear combination and choosing probable transmitted signals that minimize a minimum mean squared error function, the signals of the various terminal units are canceled when detecting the signal of a particular unit. In another embodiment of the invention, the basic approach is used to obtain an initial estimate of the signals transmitted by one terminal unit, and the contribution of those signals is removed from the received signals prior to detecting the signals of other terminal units.

Abstract: The invention relates to method and code generator for updating linear feedback shift register (LFSR). The method comprises defining jumps corresponding to different powers of two for shifting from known state to new state. Then in each jump the LFSR obtained as a result of the jump in question is generated: the value of one element of the obtained LFSR is generated from the previous state and the pre-stored mask register corresponding to said obtained element, while the mask register determines the elements of the LFSR of the previous state, using which elements said element value is generated, and the generation of the value of one LFSR element is repeated for each remaining obtained feedback LFSR by shifting the mask register to the position of said remaining element and by generating the value of said remaining element of the obtained LFSR from the previous state and the shifted mask register.

Abstract: In a multi-carrier transmission system, a clock timing error (&tgr;e) is calculated at the receiver's side and used for synchronization between a transmitting modem and a receiving modem (RX1). The clock timing error (&tgr;e) is calculated from phase errors (&phgr;0, &phgr;1, . . . , &phgr;i, . . . , &phgr;N-1) detected for a plurality of pilot carriers during a tracking mode in such a way that the share (Ai) of a phase error (&phgr;i) detected for a particular pilot carrier in the clock timing error (&tgr;e) depends on the transmission quality (SNRi) of that pilot carrier over the transmission medium in between the two modems. In this way, the robustness of the synchronization for narrowband noise near a pilot carrier is improved significantly.

Abstract: A radio frequency receiver includes an amplifier and a detector that produces a bias control signal based on a signal environment. A bias level of the amplifier is set according to the bias control signal. Bias levels of other receiver circuits may have similarly adjusted bias levels, including buffers, IF oscillators, mixers, and converters. The invention can be used to increase range of linearity, intermodulation immunity and reduce power consumption by reducing the bias level under typical conditions and relying on the bias control to increase bias levels under adverse signal conditions. The invention has advantages where power is at a premium, particularly when a device is in standby mode, including mobile, portable and hand held pagers and wireless telephones and Internet connections. If standby mode operation in non-maximum signal environments dominates the usage of the receiver, then the invention can substantially increase battery life.

Abstract: I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by &pgr;/4, 2&pgr;/4, and 3&pgr;/4 counterclockwise.

Abstract: A technique for identifying the encoding law utilized by a central office codec may be implemented in a receive modem. The encoding law, which is typically dictated by the country in which the central office is located, is employed to generate a plurality of transmission levels during an initialization period associated with the modem system. The receive modem analyzes a number of these transmission levels to determine whether the levels have certain characteristics associated with the particular encoding law followed by the central office codec. When the receive modem detects the codec type, it may transmit a suitable identifier back to the transmit modem.

Abstract: A system for the estimation of the complex gain of a transmission channel is designed for parallel type modulators/demodulators that can be used in digital radio broadcasting. The system includes a given number N of sets of interpolators to estimate the gain on a useful symbol from known symbols constituting gain references evenly positioned in the transmitted signal, each set of interpolators being adapted to a particular situation of reception, ranging from a stable single-path channel to a channel with high temporal dispersion and high instability. The outputs of the interpolators are coupled to a selection device programmed to choose the set of interpolators that gives the weakest estimated noise during a specified length of time. Such a system may find application to digital radio transmission.

Abstract: A multipath processor processes a plurality of groups of spread-spectrum signals. Each group has a plurality of spread-spectrum signals. A first plurality of spread-spectrum signals is despread within a first group to generate a first plurality of despread signals. The first plurality of despread signals are combined as a first combined-despread signal. A second plurality of spread-spectrum signals is despread within a second group to generate a second plurality of despread signals. The second plurality of despread signals are combined as a second combined-despread signal. The first and second combined-despread signal are combined as an output-despread signal.

Abstract: A method of, and receiver for, recovering data bits from a spread spectrum signal, in which a digitally sampled chip sequence is derived from a received spread spectrum signal, a matched filter (34) filters the digitally sampled chip sequence in a matched filter, a circuit (36) obtains a running average of the output from the matched filter over successive bit periods, and means are provided for noting, in successive bit periods, which of the matched filter output samples corresponds to the maximum value in the running average and determines the sign of the sample in a stage of the matched filter synchronised with the maximum value and assigns a data bit value in accordance with the sign.

Abstract: A digital DC offset correction circuit (68) provides DC offset correction within a receiver (50) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit (68) includes an integrator (90), a low pass filter (92), a decimator (94), a digital to analog converter codeword clamp (96), and a digital to analog converter (98).

Abstract: A method for demodulating a carrier wave that is modulated using a digital symbol sequence and that is transmitted over a noise-impacted channel, the ideal edge shapes of possible transitions between two symbols being known and stored in memory as reference edges, and a received edge being scanned and digitalized using a scanning frequency that is a multiple of the frequency of the symbol sequence. In particular, for detecting a received and scanned edge, all scanning values are used for calculating Euclidean distances from at least two reference edges, and the reference edge associated with the lowest Euclidean distance is selected. A Viterbi algorithm is applied to a sequence of estimated edges (rather than to an estimated symbol sequence) and the specific Euclidean distances between the edge received in one symbol period and the reference edges are considered as the costs of one trellis branch of the Viterbi algorithm.

Abstract: To provide a high speed digital PLL circuit which is easily manufactured by IC process. The phase of data signal is locked with a first clock of which frequency is the half of the data signal. Further, a second clock of which phase is shifted by &pgr;/2 compared with the first clock is used for determining phase delay or phase advance of the data signal compared with the first clock. VCO outputs the first clock and the second clock. The phase comparator for inputting the data signal, the first and second clock, outputs a first data sampled at rise up of the first clock, a second data sampled at fall down of the first clock, a first indication signal indicating the phase delay, and a second indication signal indicating the phase advance. The filter for inputting the first and second indication signal outputs a control voltage for VCO.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode.

Abstract: A method of estimating the frequency at the receiving end for a packet transmission system, for estimating a carrier frequency error between received symbols (rk) and transmitted symbols (ck). An error function (H(&Dgr;{circumflex over (f)})) defined for minimizing a magnitude which is representative of an average distance between the received symbols compensated in phase (r′k) and estimations of the received symbols affected by a frequency error estimation (ĉkej2&pgr;k&Dgr;{circumflex over (f)}) is computed. The estimations of the received symbols affected by the frequency error estimation are obtained by varying the frequency error (&Dgr;{circumflex over (f)}) in an acquisition interval ([−fmax, +fmax]) for estimations of the transmitted symbol (ĉk). The estimations of the transmitted, symbols (ĉk) are obtained based on a threshold relating to the phase of the received symbol which is compensated in phase (r′k), in the case of a modulation of the PSK type.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter. Such a method and apparatus include processing that begins by receiving an input digital stream at a first clock rate from an oversampling quantizer (e.g., a sigma delta modulator). The processing continues by integrating the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal. The processing continues by determining when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value. The processing continues by, when the difference is within a targeted range (e.g.

Abstract: The invention relates to a method and a generator for generating a short orthogonal spreading code in CDMA radio system. The method includes obtaining control data the length, the running number and the code class of the spreading code. A spreading code is formed such that the running number of the spreading code in the code class is first denoted by a binary code number of the same length as the code class. Thereafter, a modified code number is formed by reversing the code number. The following operations are repeated for each chip Of the spreading code: the running number of the chip is denoted by a binary chip number of the same length as the code class, and a binary sum is formed with an AND operation between the modified code number and the chip number, and one value is formed for the chip of the spreading code with an XOR operation between all the bits of the binary sum.

Abstract: Input data is converted into digital data in a A/D converter in synchronization with a regenerated clock, a zero-cross detecting signal of the digital data is detected in a zero-cross detector, a phase shift quantity is detected in a phase detector according to two pieces of digital data obtained before and after the detection of the zero-cross detecting signal, an average of phase shift quantities is calculated as target oscillation frequency data in a frequency calculating unit, the target oscillation frequency data is converted into analog data in a D/A converting unit, and the regenerated clock is generated in a voltage control oscillator according to the analog data and is provided for the A/D converter. Thereafter, the digital data is decoded to regenerated data in a Viterbi decoder in synchronization with the regenerated clock.

Abstract: A decoding method and apparatus include providing capability for decoding data symbols that were encoded in a transmitter by either a serial-concatenated code or turbo code in a parallel processing fashion. The receiver upon knowing the encoding method may reconfigure the selection of data symbols from a table (600) to accommodate the appropriate decoding process. Initially a data symbol estimate for a number of data symbols of a plurality of data symbols Xi, Yi, and Wi are determined. The estimates of data symbols Xi, Yi, and Wi passing to a first and second decision nodes (610, 620) include estimates for the variables in one or more encoding equations. A new estimate for the data symbol Xi is determined based on the estimate determined at the initial step and the new estimate for each occurrence of the data symbol Xi at the first and second decision nodes (610, 620).

Abstract: The invention relates to a system for transmitting packets from interactive terminals to a head station. The terminals intended for consumers are provided with local oscillators which are not very accurate and use carriers having frequency errors which are relatively large with respect to the theoretical reference value (Fp). The invention provides an improvement of the reception of signals having such a frequency shift at the receiver end. To this end, the invention provides a method of estimating the frequency error &Dgr;{circumflex over (f)}, which consists of rapidly obtaining the maximum value of a discrete error function denoted Z(&Dgr;{circumflex over (f)}) for a given accuracy (Acc) by computing the function Z(&Dgr;{circumflex over (f)}) for a minimal number of points.