Abstract: A method (200) of decoding a multi-level synchronous protocol having a first portion encoded as M/2-level signals and a subsequent portion encoded as M/2-level signal or M-level signals, wherein the M/2-level signals have expected larger than normal variation of deviations includes steps of decoding (202) the first portion using a biased mode which uses M correlators shifted (204) to adequately cover the frequency range of the expected larger than normal variation of deviations and determining (206) from decoding of the first portion whether the subsequent portion is the M/2-level or M-level signal. If a M/2-level signal is found, continue decoding (210) in the biased mode. If it's the M-level signal, then decoding continues in standard mode (214), which uses M correlators that are spaced in frequency to match M spectral deviations within a predetermined frequency range.

Abstract: A burst classifier is useful in a digital communication system transmitting a signal burst of a plurality of different burst types. The burst classifier includes a plurality of filters associated with the plurality of different burst types, respectively. Each filter generates correlation data based on the signal burst and a respective plurality of reference signals offset by a plurality of time offsets. The respective pluralities of reference signals are indicative of a corresponding burst type of the plurality of different burst types. A comparator then analyzes quantities based on the correlation data from each filter to determine the burst type of the signal burst.

Abstract: A modulator is configured with a first multiplexer having a first data signal input coupled to receive the first digital baseband signal and a second data signal input coupled to receive the second digital baseband signal. The first multiplexer provides a multiplexed output signal including components of the first and second digital baseband signals. The modulator also includes a source of alternating samples of first and second carrier signals and a multiplier having a first input coupled to the output of the first multiplexer and a second input coupled to the source of carrier signal samples. The multiplier is thereby coupled to provide a digital modulated output signal. The source of alternating samples of first and second baseband signals may include a second multiplexer having a first signal input coupled to receive a first carrier signal and a second signal input coupled to receive a second carrier signal.

Abstract: An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read signal. A data quantity measuring device measures a data quantity representing a quantity of data stored in the memory device. A read signal generating device generates the read signal at a frequency that varies depending upon the measured data quantity. A sampling frequency conversion apparatus comprises the memory device, data quantity measuring device, and read signal generating device employed in the asynchronous signal input apparatus. Further, the read signal generating device includes a converter which performs non-linear conversion on the data quantity measured by the data quantity measuring device.

Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic.

Abstract: A dual-mode receiver uses a hybrid cost function that provides for automatic constellation phase recovery regardless of whether a CAP signal or a QAM signal has been transmitted. In one embodiment, the receiver uses a hybrid cost function that is the superposition of a QAM-based cost function and a CAP-based cost function. In another embodiment, the receiver comprises an adaptive filter that alternates between a QAM-based cost function and a CAP-based cost function. In addition, a method is described that uses information about (a) the expected constellations, and (b) the values before and after a rotator of the receiver for deciding what type of signal is being received.

Abstract: A method and arrangements for extracting a plurality of clock signals for signal-processing circuits, in particular for a digital modem, from a supplied clock signal, for the clock signals to be extracted to be formed in each case from an output signal of an accumulator of predefined bit width n. The accumulator accumulates in each case an increment in the clock pulse of the supplied clock signal and, in the process, performs a modulo2n operation.

Abstract: A system for reducing internal interference in a radio-frequency (RF) receiver includes providing a plurality of time slots within a frame where the receiver is configured to receive external RF signals during a receive time slot within the frame. External RF signals are the prevented from reaching a front-end portion of the receiver and the receiver is activated, and a predetermined period of time is permitted to elapse to permit the receiver to settle. An interference data collection is performed during a period of time prior to a predetermined receive time slot where the data collected represents internally generated interference signals. The data collected during the interference data collection is processed to determine a bias value corresponding to the interference signals, and the receiver is then permitted to receive external RF signals during the predetermined receive time slot so that data is collected during the predetermined receive time slot.

Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence.

Abstract: A received symbol sequence is very accurately restored in a highly efficient manner with a simple configuration, wherein, respective bits of an information bit sequence are inputted to a cyclic register composed of the same number of registers as the number of bits of the information bit sequence. Signals read from the cyclic register are processed to generate a plurality of symbols. The processing is repeated each time the respective bits of the information bit sequences are shifted to the next registers, until the respective bits shift all over the registers for one cycle. All symbols generated by the process are transmitted as a symbol sequence. Symbols of a received symbol sequence are respectively inputted to a first register group composed of the same number of registers as the number of symbols of the symbol sequence.

Abstract: The present invention discloses a method and apparatus for thresholding an input signal synchronous with a clock signal at a receiver. The input signal is compared with a threshold voltage to produce a difference signal. The difference signal is synchronized with the input signal to generate a feedback signal. The threshold voltage is adjusted based on the feedback signal.

Abstract: In a digital frequency phase locked loop (FPLL) for a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, the digital FPLL for a VSB transmission system having a VCO and a plurality of NTSC carrier eliminating filters for eliminating interference of NTSC adjacent channels includes a filter for eliminating high-frequency components by converting a digital signal output from one of the plurality of NTSC carrier eliminating filters, a delay for delaying the high-frequency-component-eliminated signal by a predetermined width so that its frequency-versus-phase characteristics are changed linearly, symbol inverter for inverting the symbol of the digital signal output from another of the plurality of NTSC-carrier eliminating filters, a switch for selectively outputting the symbol-inverted signal and the digital signal output from another filter, a second filter for limiting the selectively output signal to a predetermined frequency band, a digital-to-analog (D/A) conver

Abstract: A system and method for measuring jitter. One class of embodiments is particularly useful for testing the aperture jitter of a high speed Analog to Digital (A/D) converter. Aperture jitter in a Sample and Hold circuit (S/H) or in an A/D converter introduces noise into the sampled signal, which is more extreme in areas of the input waveform that have a steep positive or negative slope. The preferred embodiment allows an easy and inexpensive way to measure aperture jitter in S/H and A/D circuits. The technique can also be adapted for measuring edge jitter in digital clock signals or in analog sine wave signals.

Abstract: An auto frequency control apparatus arranged to vary the division ratio of the comparison signal portion in the phase comparator with the AFC control voltage so as to change the frequency in order to make coincide the frequency of the output signal from a local oscillation portion and that of a carrier-wave signal for a frequency-shift keying signal with each other. The frequency of an output signal from a reference-signal generating portion is divided by a divider 213. The frequency of the output signal from a local oscillation portion is supplied to an auto frequency control 202. A control-signal processing portion 207 receives AFC control voltage to instruct an updown counter 205 to correct the division to correspond to the voltage. In accordance with the instruction, a counter 203 divides the supplied signal, the signal being multiplied with an integer in a multiplier 204 so as to be transmitted. The output signal is divided with a division ratio set by a divider 209.

Abstract: A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the channel, to restore from the transmitted program data a highly accurate program clock signal from which the jitter is removed. The regenerator includes a buffer for temporarily storing transmitted data received over the channel. A read clock selector monitors the buffer to determine the amount of the transmitted data stored in the buffer, and selects one of read clock signals in response to the data amount. A program clock acquisition circuit reads out the transmitted data from the buffer in response to a read clock signal selected by the selector, and restores the clock signal of the program data from the transmitted data.

Abstract: A carrier control loop (1) for a receiver of digitally transmitted signals is disclosed comprising, in the direction of signal flow, a quadrature demodulator (3), a symbol recognition device (4), a detector (9) for forming a phase deviation value (&phgr;d) and/or a frequency deviation value (fd), a feedback device (10), and a variable-frequency oscillator (11) connected to the quadrature demodulator (3). An evaluating device (12) determines from signals (I, Q) of the carrier control loop (1) a reliability value (z) for the measured phase deviation value (&phgr;d) and/or frequency deviation value (fd), and controls the carrier control loop (1) in accordance with the determined reliability value.