Abstract: In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.

Abstract: A semiconductor arrangement including a substrate, a dielectric layer, and a semiconductor layer disposed between the substrate and the dielectric layer. The arrangement further includes an ohmic contact including a plurality of metal contact fragments located in a plurality of trenches formed in the dielectric layer, and a metallic connector layer electrically connecting the metal contact fragments. The ohmic contact electrically connects the metallic connector layer to the semiconductor layer.

Abstract: There is provided a film forming method including: supplying a halogen-free silicon raw material gas and a halogen-containing silicon raw material gas into a processing container while lowering a temperature of a substrate accommodated in the processing container from a first temperature to a second temperature in a temperature lowering process; and supplying the halogen-free silicon raw material gas and the halogen-containing silicon raw material gas into the processing container while maintaining the temperature of the substrate at a third temperature in a temperature stabilizing process, that occurs after the temperature lowering process.

Abstract: The present disclosure provides a vertical memory structure with air gaps and a method for preparing the vertical memory structure. The vertical memory structure includes a semiconductor stack including a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

Abstract: A display substrate having a display area and a gate-on-array (GOA) area outside the display area is provided. The display substrate includes a base substrate; a light shielding layer on the base substrate; an insulating layer on a side of the light shielding layer away from the base substrate; and a GOA signal line on a side of the insulating layer away from the light shielding layer, and is connected electrically in parallel with a first part of the light shielding layer, the first part being in the GOA area. The display substrate includes a plurality of first vias extending through the insulating layer in the GOA area. The GOA signal line is electrically connected to the first part of the light shielding layer through the plurality of first vias respectively, thereby connecting the GOA signal line and the first part of the light shielding layer electrically in parallel.

Abstract: Implementations described herein provide a method for calibrating a temperature of a substrate support assembly which enables discrete tuning of the temperature profile of a substrate support assembly. In one embodiment, a system, comprises a memory, wherein the memory includes an application program configured to perform an operation on a substrate support assembly, a control board disposed in a substrate support assembly, wherein the control board comprises a processor having an wireless interface, a pulse width modification (PWM) heater controller, wherein the processor is connected with the memory to read and access the application program from the memory when in operation, and a heating element coupled to the pulse width modification (PWM) heater controller, wherein the heating element comprises a plurality of spatially tunable heaters that are individually tunable by the pulse width modification (PWM) heater controller.

Abstract: A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

Abstract: An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first conductive layer, first and second pillars. The substrate includes first to third regions. The first pillars are provided in the first region to penetrate the first conductive layer. The second pillars are provided in the second region or the third region to penetrate the first conductive layer. The second region includes first and second sub-regions. The first sub-region includes a contact corresponding to the first conductive layer. A coverage of the second pillars in the second sub-region is higher than a coverage of the second pillars in the first sub-region and lower than or equal to a coverage of the first pillars in the first region.

Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Abstract: [Object] To make it difficult for components other than films to be contained in a lamination interface. [Solving Means] In a deposition apparatus, a vacuum chamber includes a partition wall which defines a plasma formation space and includes quartz. An deposition preventive plate is provided between at least a part of the partition wall and the plasma formation space and includes at least one of yttria, silicon nitride, or silicon carbide. On a support stage, a substrate including a trench or hole including a bottom portion and a side wall is capable of being disposed. A plasma generation source generates first plasma of deposition gas including silicon introduced into the plasma formation space to thereby form a semiconductor film including silicon on the bottom portion and the side wall. The plasma generation source generates second plasma of etching gas including halogen introduced into the plasma formation space to thereby selectively remove the semiconductor film formed on the side wall.

Abstract: A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.

Abstract: A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.

Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.

Abstract: Methods and systems for enhancing workflow performance in the oil and gas industry may estimate the properties of drilling muds (e.g., density and/or viscosity) located downhole with methods that utilize real-time data, estimated drilling mud properties, and mathematical models. Further, the methods described herein may optionally account for the uncertainties induced by sensor readings and dynamic modeling.

Abstract: In a method, a charged metal dot is deposited on a first position of a surface of a semiconductor substrate. Then, a charged region is formed on a second position of the surface of the semiconductor substrate, thereby establishing of which an electric field direction from the first position toward the second position. The first position is spaced apart from the second position by a distance. Thereafter, a precursor gas flows along the electric field direction on the semiconductor substrate, thereby forming a carbon nanotube (CNT) on the semiconductor substrate.

Abstract: A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer.