Abstract: A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal molded body 2 as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer 3a with regions of varying thickness. The metal molded body 2 takes the form here of a flexible contacting film 5 of such a thickness that this contacting film is sintered with its side 4 facing the sintering layer 3a onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal molded body.

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Abstract: A display device comprising a first electrode that comprises a first region, a second region, and a third region located between the first region and the second region; a first insulating film disposed on the first electrode; a second electrode that is disposed on the first insulating film and comprises a fourth region overlapping the third region; a second insulating film disposed on the second electrode; a contact hole formed through the second insulating film, the first contact hole exposing the first, second and fourth regions; and a third electrode that is disposed on the second insulating film to cover the first contact hole, and is connected to at least one of the first region and the second region exposed by the first contact hole and the fourth region exposed by the first contact hole.

Abstract: A light-emitting diode package structure, a light-emitting device and a method of making the same are provided. The light-emitting diode package structure includes an insulating base, a first conductive unit, a second conductive unit and at least one light-emitting diode chips. The first conductive unit is disposed on the insulating base. The second conductive unit is disposed on the insulating base and separated from the first conductive unit. The at least one light-emitting diode chips is electrically connected to the first conductive unit and the second conductive unit. Further, the first conductive unit has a first groove, and an outer surface thereof is divided by the first groove into two separated parts. In addition, the second conductive unit has a second groove, and the outer surface thereof is divided by the second groove into two separated parts.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.

Abstract: A light emitting diode chip comprises a light emitting diode chip core and a coating layer. The coating layer covers side surfaces of the light emitting diode chip core. And a display composed of the light emitting diode chips is also provided.

Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Abstract: A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region provided on the substrate. The pad region is configured for mounting an electronic component, and comprises a plurality of pads spaced from each other and traces connected to their respective pads. At least one of the pads has an arc edge. In the present invention, the distance between the pads is easy to be controlled during fabrication, and the stability of the adhesion between the chip and pad region is enhanced.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same, a semiconductor module, and an electronic device capable of more certainly improving an optical characteristic and chromatic aberration. A semiconductor package provided with a pedestal having a cylindrical shape including a curved surface curved so as to be concave to a light incident side, and a linear image sensor on which a plurality of pixels each including a photoelectric conversion element is arranged in a one-dimensional direction, the linear image sensor fixed on the curved surface on which a light-receiving area formed of a plurality of pixels is curved so as to be concave to the light incident side is provided. The present technology may be applied to the semiconductor package used in an image reading device, for example.

Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

Abstract: An optoelectronic component includes a housing, wherein a cavity is formed on an upper side of the housing, which is delimited by a wall, the housing has an empty space, the wall is arranged between the cavity and the empty space, the housing has a surface, the empty space is arranged between the surface of the housing and the wall, the wall and the surface are arranged at least partially parallel to each other, the wall includes an optically transparent material, and the wall has a wall thickness of 1 ?m to 100 ?m.

Abstract: A micromechanical device that includes a first substrate, at least one first cavity, and a sealed inlet to the first cavity, the inlet extending through the first substrate. The inlet includes a laser-drilled first subsection and a plasma-etched second subsection, the plasma-etched second subsection having an opening to the first cavity, and the inlet in the first subsection being sealed by a molten seal made of molten mass of at least the first substrate. A combined laser drilling and plasma etching method for manufacturing micromechanical devices is also described.

Abstract: A light emitting device includes a base and a light emitting diode chip, the light emitting diode chip is formed on a top surface of the base, an outline of a projection of the light emitting diode chip projected on the top surface of the base is positioned in the top surface of the base. The light emitting device further includes a light reflecting portion, the light reflecting portion is formed on the top surface of the base, the light reflecting portion is defined around the light emitting diode chip, a height of the light reflecting portion is less than a height of the light emitting diode chip.

Abstract: A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to the first surface, a terminal disposed adjacent to the first surface and connected to the electrode on the first surface through a bonding member, and a heat sink disposed adjacent to the second surface and connected to the electrode on the second surface through a bonding member. The first surface is a (0001) plane and a thickness direction of the semiconductor chip corresponds to a [0001] direction. Of the distances between the end portions of the semiconductor chip having a square two-dimensional shape and the end portions of the terminal having a rectangular two-dimensional shape, the shortest distance L1 in a [1-100] direction is shorter than the shortest distance L2 in a [11-20] direction.

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/?10 degrees.

Abstract: Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween.

Abstract: A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.