Abstract: A chip reducing thermal stress of current path thereon, including: a substrate having at least one nanowires zone formed on a surface thereof; and at least one current path formed within the at least one nanowires zone on the surface of the substrate, wherein, the at least one nanowires zone has a function of reducing a thermal stress of the at least one current path.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

Abstract: A bonding structure of a chip and an electronic circuit contains: a chip holder, a chip accommodated in the chip holder, multiple conductive feet electrically connected with the chip, and an electronic circuit. The chip and the multiple conductive feet are covered by a packaging material, and a part of each of the multiple conductive feet exposes outside the packaging material to form an extension. The electronic circuit includes a porous substrate and an electric circuit connected on the porous substrate, wherein the electric circuit is formed from conductive inks which penetrate into the porous substrate, and the extension is inserted through the electric circuit, hence the extension is electrically connected with the electric circuit.

Abstract: Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes respective first portions on sidewalls of first hardmask sections previously formed on a substrate, a recess between the first portions on the sidewalls of each adjacent pair of the first hardmask sections, and a second portion between the substrate and the recess. The conformal layer is constituted by a second material chosen to etch selectively to the first material constituting the first hardmask sections. A spacer is formed in each recess and masks the respective second portion of the conformal layer. The conformal layer is then etched to form second hardmask sections each comprised of one of the second portions of the conformal layer. The substrate is etched with the first and second hardmask sections masking the substrate to form a plurality of fins.

Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.

Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.

Abstract: Provided are a package substrate and a light emitting device package. The package substrate may include a base substrate having a plurality of mounting regions and a plurality of unit light emitting regions which include at least one of the plurality of mounting regions, a plurality of first circuit patterns disposed on the base substrate and connected to a plurality of light emitting devices in the plurality of mounting regions, a plurality of second circuit patterns connected to the plurality of unit light emitting regions, and a wire electrically connecting the plurality of second circuit patterns to the plurality of second circuit patterns, each of the plurality of second circuit patterns being connected to different unit light emitting regions, or electrically connecting the plurality of first circuit patterns to the plurality of second circuit patterns.

Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.

Abstract: Pure spin current devices are provided. The devices include sandwich structures of metal/magnetic insulator/metal. A first current injected in a first metal layer generates a pure spin current. The spin current can be switched between “on” and “off” states by controlling an in-plane magnetization orientation of the magnetic insulator. In the “on” state, the pure spin current is transmitted from the first metal layer to the second metal layer, through the magnetic insulator layer. The pure spin current in the second metal layer induces generation of a second charge current. In the “off” state, the pure spin current is absorbed at the interface between the first metal layer and the metal insulator. Such structures can serve as pure spin current valve devices or provide analog functionality, as rotating the in-plane magnetization provides analog sinusoidal modulation of the spin current.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a source in electrical communication with the substrate. A drain is also in electrical communication with the substrate. A gate overlies the substrate between the source and the drain, wherein a channel is defined within the substrate directly underlying the gate, and where a Schottky portion of the substrate is positioned between the channel and the source.

Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.

Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.

Abstract: A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes forming a first patterned conductive layer. The method also includes forming a dielectric layer covering the first conductive layer. The method further includes forming a conductive via in the dielectric layer. In addition, the method includes forming a resistor layer and a protection layer over the dielectric layer. The method also includes patterning the protection layer to form a protection feature and patterning the resistor layer to form a resistor feature overlapping the first conductive layer. The resistor feature is electrically connected to the first conductive layer through the conductive via. The method further includes forming a second conductive layer over the dielectric layer. The top surface of the resistor feature maintains covered by the protection feature during the formation of the second conductive layer.

Abstract: Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.

Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a memory region and a logic region. A lower metal layer is disposed over a substrate, and comprises a first lower metal line within the memory region. An upper metal layer overlies the lower metal layer, and comprises a first upper metal line within the memory region. A memory cell is disposed between the first lower metal line and the first upper metal line, and comprises a planar bottom electrode. The planar bottom electrode abuts a first lower metal via of the lower metal layer. By forming the planar bottom electrode and connecting the planar bottom electrode to the lower metal layer through the lower metal via, no additional BEVA planarization and/or patterning processes are needed. As a result, risk of damaging the lower metal lines are reduced, thereby providing more reliable read/write operations and/or better performance.

Abstract: A display apparatus includes a display panel, a driver, a controller and a first flexible substrate. The display panel includes first and second substrates facing each other. The first substrate includes a switching element connected to a pixel electrode. The driver provides a driving signal to the display panel. The controller provides a control signal to the driver. The controller includes first and second printed circuit boards spaced apart from each other. The first flexible substrate electrically connects the first and second printed circuit boards to each other. The first flexible substrate defines a first contact portion at which the first flexible substrate is connected to the first printed circuit board, a second contact portion at which the first flexible substrate is connected to the second printed circuit board, and an overlap portion overlapping the display panel and at which the first flexible substrate is attached to the display panel.