Abstract: A circuit arrangement of a memory testing apparatus provided with a mask pattern memory is simplified. A mask pattern data read out of a mask pattern memory 111 is directly fed to a mask circuit 113 without converting the bit arrangement of the mask pattern data into a bit arrangement conforming to the arrangement of terminals of a memory under test 200. Temporary failure data having a bit arrangement corresponding to the arrangement of terminals of the memory under test is applied from a logical comparator 107 to a failure data selector 108 which controls the passage of a failure data the bit arrangement of which has been converted into a bit arrangement according to a given sequence of bit significance. Failure data having passed through the failure data selector is applied to the mask circuit which functions to mask writing of failure data in a failure analysis memory 109.

Abstract: A system and method for performing set partitioning to recover M-ary modulated digital data symbols. The set partitioning technique reduces the complexity of sub-optimal algorithms in communications systems such as wireless communication systems utilizing PML, SPML, and APML algorithms. The system and method reduces the number of searches in a system by choosing an average value for the transmitted signals in the system.

Abstract: The present invention is a system and method of testing logic circuits in memory of an integrated circuit in a fraction of the time. The present invention discloses a system and method to allow testing imbedded array logic blocks in parallel, rather than sequentially. The present invention allows for the testing of multiple logic blocks associated with different memory or column locations at the same time. This technique allows for reduction in test time by a factor of X, where X is the number of rows or columns or memory cells feeding logic.

Abstract: A high capacity computer disk drive system operating a micro-hard disk drive is disclosed in which the hard disk rotates at a speed of approximately 2746 r.p.m. and in which the data received from the host computer for storage on the hard disk is converted to 2,7 RLL coding prior to being written onto the disk. The disk drive system disclosed herein has a formatted data storage capacity in excess of 10 MB and an unformatted digital information storage capacity in excess of 12.5 MB, using both sides of the disk. The micro-hard disk drive system is connected to a host computer using a Small Computer Systems Interface (SCSI) which eliminates the need to provide additional disk controller hardware and software in the host computer. The micro-Winchester disk drive system is particularly suited to meet the needs of a portable computer system.

Abstract: A method is described for generating a digital checksum signature for a collection of data. According to the method, a first operation is performed on the collection of data to generate a first encoded result. The first encoded result is used to define a first portion of the digital checksum signature. A second operation is performed on the collection of data to generate a second encoded result. The second encoded result is used to define a second portion of the digital checksum signature.

Abstract: In a semiconductor integrated circuit device having a test circuit, the test time can be shortened and further the circuit activation ratio can be increased, while reducing the circuit scale. In the operation test mode, the counter circuit (10) is divided into the first counter circuit (10a) and the second counter circuit (10b) by use of the test circuit (20). Further, the same input count clock CK is inputted at the same time to both the first and second counter circuits (10a, 10b) in parallel. The normal operation of the counter circuit (10) can be discriminated by checking whether the output signal A of the first counter circuit (10a) matches the output signal B of the second counter circuit (10b) or not.

Abstract: A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory.

Abstract: A novel parallel bit test circuit is provided to test a semiconductor memory device which comprises a number of memory cell arrays each having a plurality of memory cells, a word line provided in each memory cell array to commonly connect with the plurality of memory cells, and a plurality of I/O (input/output) lines respectively connected with the plurality of memory cells of each memory cell array. The parallel bit test circuit for testing the plurality of memory cells in parallel bits comprises a comparator for comparing the data of the memory cells with an externally input data to produce a test signal applied to a data I/O terminal.

Abstract: A parallel decompressor capable of concurrently generating in parallel multiple portions of a deterministic partially specified data vector is disclosed. The parallel decompressor is also capable of functioning as a PRPG for generating pseudo-random data vectors. The parallel decompressor is suitable for incorporation into BIST circuitry of ICs. For BIST circuitry with multiple scan chains, the parallel decompressor may be incorporated without requiring additional flip-flops (beyond those presence in the LFSR and scan chains). In one embodiment, an incorporating IC includes boundary scan design compatible with the IEEE 1194.1 standard. Multiple ones of such ICs may be incorporated in a circuit board. Software tools for generating ICs with boundary scan having BIST circuitry incorporated with the parallel decompressor, and for computing the test data seeds for the deterministic partially specified test vectors are also disclosed.

Abstract: An apparatus for accurately measuring a bit error ratio by using a viterbi decoder to improve the performance of a communication system that uses cyclic redundancy codes and trellis codes to detect and correct errors. The apparatus generates new cyclic redundancy codes and substitutes them in place of the transmitted cyclic redundancy codes by using decoded data that has been processed by a viterbi decoder. The apparatus then regenerates trellis encoded data by using reconstructed data that contains the new cyclic redundancy codes. Finally, the re-encoded data are compared with the transmitted data to calculate a bit error ratio. The apparatus consists of a viterbi decoding unit, a cyclic redundancy code regeneration unit, a cyclic redundancy code selecting unit, a cyclic redundancy code generating unit, a trellis re-encoding unit, a time delaying unit, a data comparing unit and a bit error ratio measuring unit.

Abstract: After producing a failure bit matrix made up of a square matrix of an arbitrary degree in which failure analysis results of memory cells are written as elements at positions specified by row addresses and column addresses, the produced failure bit matrix is multiplied by its degree, the values of the origin of the matrix obtained by subjecting the degree-multiplied failure bit matrix to discrete cosine transformation are calculated, and the result is outputted as the number of failures.

Abstract: Turbo-coding in a communications system involves coding/decoding information in stages in order to avoid retransmission of a full L-bit packet upon occurrence of a packet error. In addition to a set of code bits generated by an encoder using a turbo-coding scheme, a punctured set of code bits is generated and stored in transmitter memory. The original set of code bits is transmitted as an L-bit data packet to a receiver which stores received data samples corresponding to the original set of code bits. The receiver decodes the data packet using a turbo-decoder and determines whether the data packet has been received in error. If so, the received data samples are maintained in memory, and a request for more information is made. Some or all of the punctured information is then forwarded from the transmitter to the receiver.

Abstract: A multi-bit data block testing circuit and method thereof are described. The semiconductor memory device includes a multi-bit data block testing circuit for testing adjacent cell blocks using any one pattern selected from the same data pattern and a different data pattern during a multi-bit test mode. The multi-bit data block testing circuit further comprises a comparator operatively coupled to receive a data signal from each of the adjacent cell blocks. A multi-bit data block input source is interconnected with the multi-bit data block testing circuit via an input port and provides the data patterns during the multi-test mode. A multi-bit data block output receiver is interconnected with the multi-bit data block testing circuit via an output port and receives a test result indication from the comparator of the multi-bit data block testing circuit.

Abstract: A data transmission system for transmitting information data with a parity of an error correcting code for correcting an error in the information data. A read-out controller controls a transmitter to transmit information data and a parity so that each data component of the information data obtained by dividing the information data of one data block area into a plurality of data components and each parity component of the parity obtained by dividing the parity of one block area into a plurality of parity components are transmitted at intervals of each sector having a sector address. The sector is defined as an data area obtained by dividing one data block area of a predetermined data amount into a plurality of sectors each having an identical data amount.

Abstract: In a mixed signal integrated circuit containing both an analog core circuit and a digital core circuit, a plurality of dedicated analog boundary scan cells disposed around the analog core circuit are connected in series by a dedicated analog boundary scan path. A plurality of dedicated digital boundary scan cells disposed around a digital core circuit are connected in series by a dedicated digital boundary scan path. The analog and digital boundary scan paths are independent of each other. In testing the analog or digital core circuit, the boundary scan path dedicated thereto is selected so that sets of test control data or test data are shifted only in the boundary scan cells dedicated thereto. As a consequence, a test pattern is shortened and the analog or digital core circuit can efficiently be tested in a shorter period of time.

Abstract: In a failure section estimating apparatus for a sequential circuit, when it is determined that the failure section is positioned in the current stage combination circuit, an input vector estimating section estimates input vectors each of which sets to a failure state, at least a predetermined output section as a failure output section of an output boundary of a current stage combination circuit of the sequential circuit. A failure output propagation path determining section determines a failure output propagation region in the current stage combination circuit for each of the estimated input vectors to be applied to an input boundary of the current stage combination circuit. The failure output propagation region represents connection paths between the failure output section and input sections of the input boundary to which the failure output section is indirectly connected.

Abstract: There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches.

Abstract: A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A computer testing system, method, and computer program product is provided for testing one or more digital cross connect devices (DXCs) with one or more test and monitoring units (TMUs). A DXC test tool is coupled to each DXC and to each TMU. The DXC test tool sends a logical command or query to a DXC. A TMU tests the physical presence of the logical command directed to the DXC. The TMU sends a response to the DXC test tool indicating the state of the physical component. In this way, the DXC test tool tests each DXC in physical and logical dimensions. The DXC test tool can communicate over a plurality of communication links including fast channel links, human readable links, and remote control links. Routers are used to expand capacity. A single message display option for selecting between sending ASCII messages and sending binary messages. By connecting the DXC test tool to multiple DXCs, end-to-end path testing in physical and logical dimensions is performed.