Abstract: A memory testing method for providing test patterns for a memory device is provided. First, the memory is divided into a plurality of blocks and a test pattern is applied to completely test a first block. Next, the first block is filled with all `1`, and other blocks are filled with all `0`. Then, the first block is walked through the entire memory device to quickly test the memory and the function of the address decoder. The invention provides an efficient method for quickly and completely testing the semiconductor memory as well as detecting and locating all the address decoder faults. A method for selecting an optimal number for dividing a memory device into blocks is also presented to minimize the required test time.

Abstract: A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths.

Abstract: A pair of substantially identical integrated circuit elements, in the form of microprocessors, are operated in response to the same instruction and data signals that are accessed from a memory by one of the integrated circuits. The accessed instruction and data signal are supplied, via a synchronous interface, to the second integrated circuit, which operates thinking that the supplied data and instruction signals were accessed by it in response to address and control signals. The states of the two integrated circuits are applied to comparator circuitry, both via buffered paths. The comparator circuitry is operated in response to control signals produced by the first integrated circuit to effect comparison on only those signals that are valid at any particular moment in time. Clock-synchronizing circuitry is included to ensure that predetermined state transitions of the clocks used to operate the first and second integrated circuit occur within a prescribed time period.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet.

Abstract: A computationally and storage efficient method and means for correcting errors and erasures in linear cyclic coded data, especially Reed-Solomon codes, in which erasure values are ascertained exclusively as a function of syndromes and derived error location polynomials without recourse to computation of intermediate error or erasure values.

Abstract: A method and computer system for automatically determining test patterns for a netlist having multiple clocks and sequential circuits. The invention utilizes a static model of a sequential circuit and models the sequential circuit having multiple clock signals (e.g., one model is used for all multiple clock signals). The multiple clock signals include primary clock input signals and internal clock signals. The clock signals can be gated or dual edge. The invention makes use of the "iterative array representation of sequential circuits" (IAR) model for automatic test pattern generation (ATPG) but utilizes a static sequential circuit model. The invention receives user defined input clock signal waveforms and determines a cycle of clocks based thereon that statically represents all waveforms over time. The cycle of clocks is divided into frames where each frame contains stable clock values.

Abstract: A system and method for reliable transmission of information using asynchronous transfer mode (ATM) through a noisy transmission path such as a wireless or satellite transmission link. To efficiently adapt ATM to such wireless links requires the ability to discern ATM cell addresses in a high noise environment. The system and method provides multiple redundant addressing to reduce or eliminate misrouting of ATM cells transferred through such a noisy transmission link. The multiple redundancy addressing realizes multiple virtual circuits to the same destination. The multiple redundant addresses for the circuits are within the error space of a principal address used for actual transmission. Thus, the most probable error patterns occurring in the ATM address field will change the principal address to a redundant address to the same destination, thus avoiding misrouting of the ATM cell.

Abstract: The present invention is directed to a system comprised of a computer, at least one integrated circuit tester, a communications link enabling communications between the integrated circuit tester and the computer, and a computer-readable medium. The computer-readable medium contains a sequence of instructions that, when executed, create a set of tests for integrated circuit testing. The set of tests may include only those tests that are calculated to be statistically significant. A second set of tests may be created that includes only those tests that are calculated to be statistically insignificant. The computer monitors the test results and moves tests between the two sets to ensure that only statistically significant tests are in the first group and that only statistically insignificant tests are in the second group.

Abstract: A syndrome-based channel quality or message structure determiner (160) uses syndrome vectors to estimate the quality of a received signal in a variable message structure communication system. A digital signal from analog-to-digital converter (150) is separated into multiple branching paths, one for each potential message structure type. In a single path, a digital demodulator (221) demodulates the digital signal to produce a demodulated received signal. A deinterleaver (222) deinterleaves the demodulated received signal, and a symbol-by-symbol detector (2231) hard-decision detects the deinterleaved signal. For each hard-decision vector, at least one syndrome calculator (2241) calculates a syndrome vector. The syndrome vector is analyzed by a syndrome error estimator (2251) having an associated syndrome pattern memory (2271). A comparator (260) analyzes error counter totals from each syndrome error estimator.

Abstract: An apparatus for encoding digital data for storage on a data storage medium includes a non-deterministic randomizer code generator. The randomizer code generator may select different randomizer codes for different portions of the data to be stored. The randomizer code used to randomize a given portion of the data may be stored on the media for use in subsequent data retrieval.

Abstract: A fault simulation apparatus includes an MOS transistor output signal strength determining portion for extracting the conductivity type of an MOS transistor in which an event such as a variation in signal level occurs. A control signal value is obtained from a control terminal, and an input signal value is obtained from an input terminal, and output signal strength when the event occurring MOS transistor is turned ON is determined. In the apparatus, fault simulation is performed depending upon the output signal strength determined by the output signal strength determining portion.

Abstract: A memory system having a test mode which can be used to access signals internally generated by the system during its operation. The signals accessible in the test mode are not available to a standard user of the system, but can be used by a memory chip designer to determine the cause of a device failure. The memory system includes a test signal switch which is used to route one of a multitude of internal signals to an input/output (I/O) pad where the information can be accessed by a chip designer. In order to access the internal signals, the memory system is first placed into a test mode, which acts to shut off the data paths used for reading the output of the sense amplifier included as part of the data read path or for reading the contents of the status register. A signal specifying a particular test signal of interest is then input. Decode logic is used to verify the coded input signal and control the multiplexer to route a specified internal signal through the switch to the I/O pad.

Abstract: A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage. The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.

Abstract: A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.

Abstract: The semiconductor memory device of the present invention comprises a mode setting means for setting the test mode; a circuit for transferring data provided to one of the input/output pins in a group of a given number of input/output pins to each of the rest of the group when the test mode is set; a circuit provided for each input/output pin which, when the test mode is set, selectively inverting the data signal values provided to the input/output pins or retrieved from the memory cells so that the order of the specified logical addresses coincides with the order of the physical addresses of the memory cells; and a circuit for deciding whether or not the data reading operation has been properly performed from the data retrieved from the memory cells to the given number of input/output pins and for sending out a signal indicating the decision to one of the input/output pins in the group of the given number of input/output pins.

Abstract: An error correction circuit for an ATM header of an ATM cell uses a sequence of synchronous comparator circuits to generate a correction mask. The sequence of comparators, when used in a processor having a 32-bit bus, provide for near minimum processing delay at an ATM node. The error correction circuit also provides error status flags for an ATM cell processor, allowing for the processor to discard ATM cells with multiple errors.

Abstract: A quick retry operation is possible by outputting an error flag pertaining to a sector after error correction processing of digital data. When an output of an error detection flag unit for a correction block indicates the existence of an uncorrectable error, the sectors are checked to see if the sectors corresponding to retrieved data include any error or not based on output from a sector error flag register B. When the sectors are judged as error, signals are retrieved again from a storage medium, restored in a memory, and an error correction processing is repeated again. The data such as that of P pictures or B pictures of MPEG which can be reproduced even with errors are output even when the error detection flag unit indicates the existence of the uncorrectable error. It enables identification of the sectors with the errors and simplifies the following operations pertaining to the error at a data receiving side by outputting the error flag along with the data.

Abstract: A Cyclic Redundancy Check (CRC) code word except a fixed pattern is provided to a code data input terminal of a division circuit in synchronization with a clock signal and divided at the division circuit, then, a remainder data of the division result is outputted from output terminals. The remainder data outputted from the output terminals is compared with a CRC inherent value at a comparison circuit, and a comparison result signal indicating whether the CRC code word includes errors is outputted. A temporary memory means takes in the comparison result signal in response to rise of a clock signal inputted into a clock signal input terminal, temporarily stores it, then output its storage contents as an error detecting signal via an output node.

Abstract: A method is described by which a data communication network can be tested. The network consists of a number of nodes which are connected to each other. At least one of the nodes is designated to the user as be inaccessible from a first node (A). Data are available within the network which, starting from the first node indicate the path to the node which is designated as being inaccessible. An interrogation is carried out to determine which is the nearest node, starting from the first node, on the path to the node which is designated as inaccessible. This nearest node is then directed to determine whether the interrogated nearest node is accessible. If this is the case, another interrogation is performed to determine which is the nearest node, now starting from the already reached node, on the path to the node which is designated as inaccessible. Another test is performed to ascertain if the new nearest node is accessible.