Abstract: The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors made of a first material with relatively low conductivity and each having a plurality of first electrical connection points arranged along itself and a second corresponding plurality of second conductors made of a second material with relatively high conductivity and each having a plurality of second electrical connection points arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors are interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors.

Abstract: A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.

Abstract: The present invention provides a security configuration of EEPROM, which is adaptable to a semiconductor integrated circuit. Each byte or minimum cell of the EEPROM is assigned a security bit which corresponds to the same memory cell of EEPROM in a data memory array. Since the security bit can be established inside the memory array, necessary chip area is not increased significantly.

Abstract: A semiconductor memory device comprising a plurality of memory cell arrays each of which includes a plurality of memory cells, a plurality of word lines connected to the memory cells for addressing them, a plurality of bit lines connected to the memory cells for transferring data from/to them, a first word line decoder connected to the word lines for activating them, and a bit line decoder connected to the bit lines for activating them. The semiconductor memory device further comprises a plurality of metal lines. Each of the metal lines is formed every four of the word lines and connected to the first word line decoder. The semiconductor memory device further comprises a plurality of second word line decoders. Each of the second word line decoders is connected to a corresponding one of the metal lines to address one of corresponding four of the word lines.

Abstract: A memory 200 comprising a plurality of rows and columns of memory cells, each column of cells associated with a conductive bitline 301. Memory 200 further includes precharge circuitry 204, 206 for precharging a selected one of the bitlines in response to a received control bit.

Abstract: A multi-write port register is provided with a local clock buffer (LCB) to control a gate on the input port to reduce potential timing hazards. The LCB provides flexible logic function and is controlled by a clock and word-line inputs. In addition, the LCB may also have bit-line and/or field mask inputs. The LCB handles all the timing critical functions that all the Word Lines (WLs) previously performed in conventional multi-write port registers, thus providing a substantial performance increase.

Abstract: A demodulator circuit which demodulates pulse-width modulated signals used for data transfer within a semiconductor integrated circuit, including a sampling signal generator that generates a plurality of sampling signals after respective different predetermined times have elapsed since receipt of a leading edge of a pulse signal, and a plurality of sampling circuits provided in corresponding relation to the plurality of sampling signals which receive the pulse signal and the sampling signals associated therewith. The plurality of sampling circuits are rendered operable after receipt of the leading edge of the pulse signal and output a detection signal indicating whether or not a trailing edge of the pulse signal is received prior to receipt of the sampling signals. An encoder then generates data depending on which sampling circuit judges that the trailing edge of the pulse signal is received prior to receipt of the sample signals.

Abstract: A column redundancy circuit and method of a semiconductor memory device. The column redundancy circuit comprises a programming element for programming a repair column address; a comparing element for comparing the programmed repair column address with a column address inputted from outside to thereby generate a redundancy enable control signal according to result of the comparison; a decoding element for decoding the repair column address signal to thereby generate a decoding signal; and a redundancy column select element for compounding the decoding signal and a data input signal to thereby enable a redundancy column select signal.

Abstract: A semiconductor memory comprising core blocks 1, 2, 3 and 4 each comprising memory cell arrays each having a plurality of memory cells in a matrix and sense amplifiers and decoders accompanying the memory cell arrays. An inter-block region is arranged among the core blocks wherein data signal lines, address signal lines and control signal lines are provided. Pad arrays IO Pad and A Pad each comprising a plurality of pads and buses IO Bus and A Bus are arranged among the core blocks. The buses A Bus are jogged in a connection region. The buses IO Bus and A Bus are arranged successively in the inter-block region and the data signal lines, the address signal lines and the control signal lines are connected to the buses A Bus and IO Bus in the inter-block region.

Abstract: In a semiconductor memory device including ROM cells, a digit line for receiving read data from a selected one of the at the memory cells, and a bias circuit for amplifying a voltage at the digit line, a differential amplifier, which has a positive phase input, a negative phase input, a positive phase output and a negative phase output, is provided. The positive phase input is connected to the output of the bias circuit. The negative phase output is connected to the negative phase input, thereby establishing a positive feedback loop in the differential amplifier.

Abstract: A dual clock Read circuit for a memory array having a first latch that is set in response to a data ready signal and a second latch that is set in response to a first clock signal. Logic circuitry generates a second clock signal when the first and second latches are set. A third latch is set in response to the second clock signal for latching the data from the memory array before it is forwarded to an off-chip driver.

Abstract: A word line decoder gate including a plurality of parallel-coupled devices coupled to a common node for receiving and decoding an address upon assertion of a clock signal, where each parallel device receives a corresponding address signal or its inverted counterpart depending upon the particular address being decoded. A precharge device is coupled to the common node for keeping it at a first voltage level until the clock signal is asserted, and two series coupled charge devices are coupled between a source voltage and the common node, which charge devices attempt to charge the common node to a second voltage level during a time period while the clock signal is asserted and a delayed clock signal remains deasserted. A delay device receives the clock signal and asserts the delayed clock signal. However, any one or more of the parallel devices, if activated, provides a current path from said common node to override the two charge devices to keep the common node substantially at the first voltage level.

Abstract: A method of operating a memory device including a plurality of data/address input/output terminals, an array of memory cells and circuitry for accessing selected ones of the memory cells in response to received address bits. At least one row address bit and at least one column address bit are substantially simultaneously input during an address cycle, at least one of the address bits being input through a selected one of the multiplexed terminals. The memory cells addressed by the row and column bits are then accessed through selected ones of the multiplexed terminals during a data access cycle.

Abstract: A superconducting active device has dual control inputs and is constructed such that the output of the device is effectively a linear mix of the two input signals. The device is formed of a film of superconducting material on a substrate and has two main conduction channels, each of which includes a weak link region. A first control line extends adjacent to the weak link region in the first channel and a second control line extends adjacent to the weak link region in the second channel. The current flowing from the first channel flows through an internal control line which is also adjacent to the weak link region of the second channel. The weak link regions comprise small links of superconductor, separated by voids, through which the current flows in each channel. Current passed through the control lines causes magnetic flux vortices which propagate across the weak link regions and control the resistance of these regions.

Abstract: A duty cycle equalization circuit equalizes the duty cycle of an incoming two-level logic driving signal and includes a CMOS current source having source electrodes connected to receive the two-level logic driving signal and having drain electrodes connected to a sawtooth signal forming path, a sawtooth wave forming circuit element, such as a capacitor, connected to the sawtooth signal forming path for forming a sawtooth waveform, a reference voltage circuit, such as a low pass filter, for generating a reference voltage level as a function of the two-level logic driving signal, and a differential comparator circuit element connected to receive the sawtooth waveform at a data input thereof, and to receive the reference voltage at a reference signal input thereof, and to put out a logical signal timed to correspond with crossings of the sawtooth signal through the reference voltage level.

Abstract: A pulse discriminating circuit discriminates narrow input pulses from an input pulse signal for eliminating output pulses corresponding to the narrow pulses from an output pulse signal thereof, and comprises a delay unit supplied with the input pulse signal for introducing predetermined time delay into propagation of the input pulse signal in synchronism with a two-phase clock signal, and an eliminating unit responsive to output signals of the delay unit and operative to produce the output pulse signal consisting of output pulses corresponding to wide input pulses, wherein the delay unit comprises early stages responsive to the two-phase clock signal for transferring the input pulse signal, and later stages responsive to a transfer signal lower in frequency than the two-phase clock signal for transferring the input pulse signal so that the predetermined time delay is prolonged without increase the stages of the delay unit.

Abstract: A circuit forms a narrow output pulse by charging a first and a second node during the relatively long interval between output pulses. When an initiating pulse is received, both nodes are discharged rapidly. An inverting amplifier which forms the circuit output has its input connected to the second node, and it produces the output pulse as the complement of the voltage level at this node. Time delay elements establish the width of the output pulse. Just before the time for the fall of the output pulse, the first and second nodes are isolated and the second node is then charged to a voltage to turn off the inverting amplifier and drop the output pulse. The initiating pulse is applied to the discharging circuit through a selected one of two paths that have different delays.

Abstract: An output circuit which is provided with an integrated circuit composed of a PNP transistor and an NPN transistor of which the base is connected to the collector of the PNP transistor, a voltage source for supplying an electric potential to the emitter of the PNP transistor and voltage dropping means provided outside the integrated circuit for making the electric potential supplied to the collector of the NPN transistor less than the electric potential of the voltage source. Thereby, an electric potential supplied to the NPN transistor can be decreased because a voltage drop is caused by an element provided outside the integrated circuit. Thus, power consumption in the NPN transistor can be decreased. Namely, power consumed in the integrated circuit can be reduced. Consequently, high packaging density of the integrated circuit can be achieved and provision of multiple channels in the integrated circuit can be realized.

Abstract: An extremely fast high-voltage driver for nanosecond-level switching of gallium arsenide PIN semiconductor devices and other reactive loads utilizes two stages of voltage level translation to permit low voltage TTL logic control signals to control the application of high voltage switching pulses to a load. The circuit utilizes an input stage responsive to TTL level signals to drive a first voltage level translating stage which produces high voltage pulses complementary to the input pulses. The increased voltage pulses are supplied through an intermediate power gain stage to provide amplification of the pulse power level. The amplified pulse is supplied to an output stage for additional level conversion to thereby provide high voltage switching signals to a PIN switch or other reactive load.

Abstract: The switch has a cross-point. The cross-point has an input buffer, a level shift and an output buffer. The input and output buffers are BJT's, the level shift is two diode connected BJT's. The voltage drops across the buffers are designed to match the voltage drops across the diodes. The cross-point is enabled by a current source forcing current through the diodes. The matching of the voltage drops is effected by the Early voltage of the BJT's as they are operated at different V.sub.ce 's. An Early voltage determinator determines the effect of the Early voltage and adjusts the current flowing from the current source to force differing bias currents through the input buffer and the diodes to make the sum of the V.sub.be 's of each more independent of Early voltage. The output impedance of the current source and the impedance of the cross-point form a resistor-capacitor network. Where the f.sub..tau.