Abstract: A signal transient improvement device includes a delay circuit (1-13) receiving an input signal (C) and having an output supplying an output signal which is a version of the input signal either delayed by a predetermined amount (T3), or delayed by a controllable amount less than or equal to the predetermined amount, and a control circuit (15-23) for controlling the delay circuit. The control circuit calculates the second derivative of the input signal to obtain a control signal, the sign of which indicates whether the input signal is to be delayed by the predetermined amount, or delayed by a controllable amount less than or greater than the predetermined amount, while the amplitude of the control signal indicates the magnitude of the controllable amount less than or greater than the predetermined amount by which the input signal is to be delayed.

Abstract: BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

Abstract: A balanced modulator for use with auto-zero networks is described. The present invention is a switched capacitor balanced modulator suitable for use in auto-zero networks where a valid input signal is available only at one phase. The present invention changes the polarity of the input signal by adjusting a switched feedback capacitor, making it possible for the switched input capacitor to sample only at one (valid) phase. The balanced modulator of the present invention may be utilized with first order auto-zero low pass filters or other switched capacitor blocks, such as gain blocks, first order high pass filters, etc.

Abstract: The present invention discloses a stepped signal generating circuit for producing stepped signals having nearly perfect sinusoidal stepped signals. The stepped signal generating circuit comprises a plurality of current mirror switching sections, each having a P type and an N type current mirror for outputting constant currents upon receiving digital signals. N-MOS transistors are provided to pass or block the output current of each switching section. The constant currents outputted from the switching sections are then controlled by a constant voltage of the constant voltage source. The final output is controlled by a constant current of a constant current source before being outputted. Accordingly, the present invention generates precise and nearly sinusoidal stepped signals.

Abstract: A diffusion resistor circuit for reducing distortion caused in a diffusion resistor. The circuit includes the diffusion resistor having a substrate, an island area including an impurity of a first polarity diffused into the substrate and a resistor area including an impurity of a second polarity diffused into the island area, a circuit for supplying a current signal through the resistor area and another circuit connecting the island area to a generally central point of the resistor area for reducing distortion of the current signal.

Abstract: Method of monitoring a clock signal includes bringing a bistable element to a first state through pulses of the clock signal and, upon the occurrence of pulses of a reference signal having a frequency lower than the frequency of the clock signal, scanning the state of the bistable element and outputting it as an output signal, and subsequently setting the bistable element to a second state.

Abstract: A high voltage switch for use in electrophoresis equipment is described. A solid state switch element is triggered by a continuous DC voltage derived from an isolated and rectified AC trigger signal. The gate of solid state element is connected by a low impedancy path to ground when the AC signal ceases.

Abstract: A fault-resistant, solid-state line driver having a pair of P-type transistors in series between a bus output and a voltage source, a pair of N-type transistors in series between the bus output and a connection to ground, and a pair of input lines, one of the input lines being connected to both the gate of the P-type transistor closest to the voltage source and the gate of the N-type transistor closest to the bus output, the other input line being connected to both the gate of the P-type transistor closest to the bus output and the gate of the N-type transistor closest to the connection to ground. Such a line driver is particularly useful in devices utilizing wafer-scale levels of integration, as the failure of any one of the driver's transistors will not result in a shorting of the bus output to either ground or the voltage source.

Abstract: Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like. Examples of the basic circuits are a successor, quantizer, adder, subtractor, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit. These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like.

Abstract: A combined CMOS/linear circuit employs a voltage reference circuit to provide a temperature compensated V.sub.REF output. The circuit includes means for switching the reference circuit off and on in response to the signal on an enable terminal. The voltage reference circuit includes a current mirror feedback which is positive in nature to provide a controlled hysteresis action. This provides noise immunity for the enable input. A digital output indicator is included to indicate the state of the reference circuit.

Abstract: An improved device for sampling signals to minimize the errors introduced in the stored samples includes first and second sampling elements whose respective sampling and holding periods are offset with respect to each other, an amplifier applying a gain G to the difference between the input voltage and the sample stored by the first element, before transmitting it to the second element, and a summing circuit for adding to the samples stored by the first element a fraction of the samples stored by the other element. The sampling errors are reduced by a factor G equal to the gain value.

Abstract: In accordance with the present invention, a heater is included on an integrated circuit, together with a circuit for controlling the heater to selectively heat the integrated circuit and control the propagation delay time of signals passing through the integrated circuit. In a specific form of the invention, the propagation delay time of signals passing through at least a portion of an integrated circuit is measured and compared with a reference propagation delay time. The heater is controlled to increase the heat it produces when the measured propagation delay time is less than the reference propagation delay time. In addition, the heater is controlled to decrease the heat it provides when the measured propagation delay time is greater than the reference propagation delay time.

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal.

Abstract: A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called "V.sub.BB -Feedback" uses "zero translation delay" direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an "extra" V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the "extra" V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the "extra" V.sub.BB input.

Abstract: A power-up 3-state circuit implemented with BiCMOS techniques is described. The circuit disables itself and draws no through current once the operating level of the applied supply voltage is achieved.

Abstract: Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

Abstract: A circuit for recirculating an inductive load's (L) discharge current through the driving power switching transistor (Tpw) utilizes a control transistor (Tc) of opposite polarity to that of the power transistor and capable of withstanding a minimum fraction (1/.beta.) of the discharge current. The circuit has the advantage of allowing recirculation of current with a fixed overvoltage independent of the value of the supply voltage, without requiring additional power devices. The circuit may also be provided with means (D1, D2 and DZ1) to turn-on the control transistor in the presence of concomitant supply overvoltages to protect the power device from dumping effects.

Abstract: A MOS current switching circuit comprises a first MOSFET, a second MOSFET, a first control circuit, a second control circuit, and an inverting amplifier. The inverting amplifier receives an output voltage of a current source to provide a feedback bias voltage to the first and second control circuit which are controlled by a control signal. The first and second control circuits are complementary operated to each other in response to the control signal to provide the feedback bias voltage to the gate electrode of the first or second MOSFET. The first or second MOSFET passes selectively a noiseless constant current from the current source toward the output terminal.

Abstract: A filter circuit uses a reversible counter to eliminate noise from an input signal which changes between high and low levels. The input signal is sampled in response to a clock signal of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

Abstract: An inductively loaded switching transistor circuit for use in the DC-DC converter includes an inductive load and a switching transistor coupled to the inductive load for conducting current flowing therethrough when the switching transistor is on. A drive circuit is provided which is coupled to the switching transistor for supplying a drive current thereto, and feedback means are provided for adjusting the amount of base drive supplied to the switching transistor from the drive circuit. The drive current is varied substantially linearly with respect to the current flowing through the inductive load.