Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

Abstract: Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract: Provided may be a display apparatus that uses oxide diodes having a nano rod structure, for example, nano-rod diodes formed of a ZnO group material. The display apparatus may include a substrate, a thin film transistor layer on the substrate, and a light emitting layer on the thin film transistor layer, wherein the light emitting layer may include a plug metal layer on the thin film transistor layer, a plurality of nano-rod diodes vertically formed on the plug metal layer, and a transparent electrode on the nano-rod diodes.

Abstract: The present invention provides an organic display device, comprising: an organic solar module for obtaining solar energy and converting the obtained solar energy into electric power, and an ultraviolet organic light emitting module driven to emit ultraviolet light by the electric power obtained from the organic solar module. The present invention can fully use solar energy and carry out ultraviolet display by combining the ultraviolet organic light emitting module with the organic solar module.

Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: A method for bonding an LED assembly (71) or other electronic package (31) to a substrate PCB containing a heat-sink (52), which utilizes layers of reactive multilayer foil (51) disposed between contacts (32, 34) of the electronic package 31 and the associated contact pads (55) on the supporting substrate PCB. By initiating an exothermic reaction in the reactive multilayer foil (51), together with an application of pressure, sufficient heat is generated between the contacts (32, 34) and the associated contact pads (55) to melt adjacent bonding material (54) to obtain good electrically and thermally conductive bonds between the contacts 32, 34 and contact pads (55) without thermally damaging the electronic package (31), heat-sensitive components (35) associated with the electronic package (31), or other the supporting substrate PCB.

Abstract: A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Abstract: A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer.

Abstract: The present invention discloses a thin-film-transistor array substrate and a manufacturing method thereof. The array substrate includes a thin-film transistor and a compensation electrode. A gate electrode of the thin-film transistor is a portion of a scan-signal line and has an opening, and the opening extends to a side of the scan-signal line. A drain electrode of the thin-film transistor is disposed correspondingly to the opening. A source electrode of the thin-film transistor extends from a side of a data-signal line and surrounds the drain electrode. The compensation electrode extends from another side of the scan-signal line and corresponds to the gate electrode. Therefore, the present invention is capable of reducing parasitic capacitance between the drain electrode and the gate electrode without increasing the resistance value of the scan-signal line.

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, masking portions of each fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, an intermediate layer and a second electrode layer. The structural body includes a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer; the first electrode layer includes a metal portion and plural opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer, having an equivalent circular diameter not less than 10 nanometers and not more than 5 micrometers. The intermediate layer is between the first and second semiconductor layers in ohmic contact with the second semiconductor layer. The second electrode layer is electrically connected to the first semiconductor layer.

Abstract: In a method for machining a workpiece, a laser beam (5) is guided across the workpiece surface by means of a beam guide (2, 51), wherein the laser beam guide comprises a first guide (2) effecting a laser beam guide at a first path speed. The laser beam guide comprises a second guide (51) simultaneously operating with the first guide, which effects a laser beam guide at a second path speed, which is higher than the first path speed.

Abstract: A wager gaming machine having software and components allowing for automatic powering on and off (also referred to as remote out-of-band power control) bypassing the need for human operator intervention is described. The gaming machine has a master gaming controller and a network interface. The interface includes an input port supporting a TCP/IP connection which can be used by another network component having the gaming machine's IP address. The gaming machine may also include a Web server operating on the input port. The Web server may receive HTTP messages on the input port even when the gaming machine is powered off. Thus, the machine is capable of receiving an HTTP message at the input port instructing the machine to power on. The gaming machine may also contain a manageability engine processor for executing an active management system software component. This component implements the Web server on the gaming machine.

Abstract: A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.

Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Abstract: Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.