Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

Abstract: A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum lower than that of the first region. The second region comprises more carriers than the first region. A difference between the energy level of the conduction band minimum of the first region and the energy level of the conduction band minimum of the second region is 0.2 eV or more. The energy gap of the first region is greater than or equal to 3.3 eV and less than or equal to 4.0 eV and the energy gap of the second region is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

Abstract: A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.

Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: A display device achieves a high resolution and a low power consumption through provision of subpixels each including a single light emitting layer and subpixels each including a plurality of overlapping light emitting layers. In the display device, it is also unnecessary to increase the number of expensive fine metal masks even for rendering of various grayscales. In addition, in the display device, different light emitting layers overlap with each other, and a charge generation layer is disposed between the overlapping light emitting layers, and, as such, emission of a secondary color can be achieved without necessity of a material for an additional light emitting layer of the secondary color.

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Abstract: A display device includes a substrate, an OLED module disposed on a first surface of the substrate, and a tracing region disposed on a second surface of the substrate. The second surface is opposite to the first surface, and the tracing region is electrically connected to the OLED module.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

Abstract: A structure includes a substrate, an isolation structure over the substrate, a fin extending from the substrate and adjacent to the isolation structure, two source/drain (S/D) features over the fin, channel layers suspended over the substrate and connecting the S/D features, a first gate structure wrapping around each of the channel layers in the stack, two outer spacers disposed on two opposing sidewalls of the first gate structure that are on outer surfaces of the stack, inner spacers disposed between the S/D features and the channel layers, and a gate-end dielectric feature over the isolation structure and directly contacting an end of the gate structure. The gate-end dielectric feature includes a first material of a dielectric constant that is higher than dielectric constants of materials included in the outer spacers and the inner spacers.

Abstract: A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.