Patents Examined by Tuan Lam
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Patent number: 7737731Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.Type: GrantFiled: July 24, 2006Date of Patent: June 15, 2010Assignee: Marvell International Ltd.Inventors: Qiang Luo, Yingxuan Li, Sriharsha Annadore, Pantas Sutardja
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Patent number: 7734003Abstract: A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.Type: GrantFiled: June 10, 2008Date of Patent: June 8, 2010Assignee: AU Optronics Corp.Inventors: Chih-Yuan Chien, Yu-Ju Kuo, Wan-Jung Chen
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Patent number: 7728646Abstract: A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower.Type: GrantFiled: December 31, 2007Date of Patent: June 1, 2010Assignee: Novatek Microelectronics Corp.Inventor: Jr-Ching Lin
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Patent number: 7728636Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.Type: GrantFiled: August 14, 2007Date of Patent: June 1, 2010Assignee: Qimonda AGInventors: Wolfgang Spirkl, Martin Brox, Holger Steffens
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Patent number: 7724864Abstract: A shift register includes a plurality of stages to output a plurality of output signals, in sequence. Each of the stages includes a driving part and a discharging part. The driving part outputs an output signal of a present stage based on one of a start signal and an output signal of a previous stage, and a clock signal. The discharging part discharges the output signal of the present stage. The discharging part includes a discharge transistor and an auxiliary transistor. The discharge transistor has a gate electrode receiving an output signal of a next stage. The auxiliary transistor has a gate electrode receiving the output signal of the next stage. The auxiliary transistor is electrically connected in series to the discharge transistor. Therefore, the chance of a malfunction is decreased, and image display quality of the display device is improved.Type: GrantFiled: August 3, 2006Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Beom-Jun Kim, Yu-Jin Kim, Byeong-Jae Ahn, Bong-Jun Lee
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Patent number: 7724042Abstract: An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.Type: GrantFiled: July 6, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Sumeet Mathur, Ankit Seedher, Preetam Charan Anand Tadeparthy
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Patent number: 7724043Abstract: A common mode controller circuit (60) for maintaining a common mode voltage (Vcm) at a first node (52) and a second node (54) in a sample-and-hold circuit receiving a pair of AC coupled differential input signals (Vinp, Vinn) includes first and second resistors (R1/R2) and third and fourth resistors (R3/R4), each set of resistors connected in series between the first and second nodes, and a differential amplifier (A1) having an inverting input terminal coupled to a third node (62) between the first and second resistors, a non-inverting input terminal coupled to a reference voltage (Vref) and an output terminal coupled to a fourth node (64) between the third and fourth resistors. The common mode voltage is sampled at the third node and the differential amplifier provides a sourcing output current indicative of the difference between the sampled common mode voltage and the reference voltage to drive the fourth node.Type: GrantFiled: July 10, 2007Date of Patent: May 25, 2010Assignee: National Semiconductor CorporationInventors: Robert J. LeBoeuf, II, Matthew Courcy
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Patent number: 7719346Abstract: Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal (10) becomes lower and thus an NMOS transistor (71) operates in non-saturation to reduce an output resistance (ro71) of the NMOS transistor (71), when a gain (Ao) of a differential amplifier circuit (60) is large, the power supply rejection ratio (PSRRLF) is also large. Therefore, even when a minimum operating voltage of the reference voltage circuit is low, the power supply rejection ratio (PSRRLF) can be made larger. In other words, since the gain (Ao) of the differential amplifier circuit (60) contributes to the power supply rejection ratio (PSRRLF), when the gain (Ao) of the differential amplifier circuit (60) increases, the power supply rejection ratio (PSRRLF) also becomes larger by the increase.Type: GrantFiled: August 15, 2008Date of Patent: May 18, 2010Assignee: Seiko Instruments Inc.Inventor: Takashi Imura
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Patent number: 7714635Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation circuit for adjusting the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature, IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.Type: GrantFiled: February 6, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David John Seman
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Patent number: 7710162Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.Type: GrantFiled: June 30, 2006Date of Patent: May 4, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Sung-Joo Ha
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Patent number: 7705665Abstract: Provided is a tuning circuit of a Gm (transconductance)-C (capacitance) filter. The tuning circuit tunes a transconductance using direct current incorporating variations of a capacitance, instead of a clock signal, in a Gm tuning mode, while using the clock signal in a capacitance tuning mode. As such, it is possible to prevent deterioration of a received signal caused by the clock signal.Type: GrantFiled: August 28, 2008Date of Patent: April 27, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Kyoung Seok Park
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Patent number: 7705661Abstract: The present invention provides a current control apparatus applied to a transistor. The transistor has a control terminal, a first terminal, and a second terminal. The current control apparatus includes a current control module, a first current mirror module, a second current mirror module, a current subtractor, and a current adjusting module. The current control apparatus provided by the present invention can be applied to a bipolar junction transistor (BJT) to prevent temperature measurement errors from occurring when using a dual current mode temperature measurement method to measure the temperature of the BJT.Type: GrantFiled: May 29, 2008Date of Patent: April 27, 2010Assignee: Feature Integration Technology Inc.Inventors: Tsung-Hsueh Li, Te-Hsun Huang
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Patent number: 7702061Abstract: A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.Type: GrantFiled: December 17, 2007Date of Patent: April 20, 2010Assignee: Integrated Device Technology, Inc.Inventors: Zhuyan Shao, Juan Qiao
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Patent number: 7697655Abstract: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.Type: GrantFiled: April 11, 2008Date of Patent: April 13, 2010Assignee: Wintek CorporationInventors: Chien-Ting Chan, Wen-Chun Wang
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Patent number: 7692475Abstract: A switch circuit is disclosed. The switch circuit comprises: a hysteresis buffer, an electric switch, a first discharge resistor, a second discharge resistor, a capacitor, a feedback resistor, a first reciprocal switch, and a second reciprocal switch. When the second reciprocal switch is turned on, a power supply voltage charges the capacitor, and thus the voltage on the signal input terminal of the hysteresis buffer is decreased. Accordingly, the voltage on the signal output terminal of the hysteresis buffer is decreased, so as to turn on the electric switch. When the first reciprocal switch is turned on, the capacitor is discharged, and thus the voltage on the signal input terminal of the hysteresis buffer is increased. Accordingly, the voltage applied to the signal output terminal of the hysteresis buffer is increased, so as to turn off the electric switch.Type: GrantFiled: August 25, 2008Date of Patent: April 6, 2010Assignee: Inventec Appliances Corp.Inventors: Shih-Kuang Tsai, Jing-Xin Liang
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Patent number: 7692458Abstract: A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.Type: GrantFiled: October 11, 2008Date of Patent: April 6, 2010Assignee: Applied Micro Circuits CorporationInventor: Mehmet Mustafa Eker
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Patent number: 7692469Abstract: In one embodiment, a voltage sense circuit receives an ac input signal and forms a rectified output voltage that is representative of the ac input signal.Type: GrantFiled: April 14, 2005Date of Patent: April 6, 2010Assignee: Semiconductor Components Industries, LLCInventor: Petr Kadanka
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Patent number: 7688131Abstract: A charge pump circuit is provided. The charge pump circuit includes a pump unit, first through sixth switches, a fly capacitor and an output capacitor. In a first period, an input voltage and a first voltage charge at least one internal capacitor of the pump unit via a first terminal and a second terminal of the pump unit. In the second period, the internal capacitor of the pump unit provides charges to the fly capacitor via the second switch and generates a first output voltage. In the third period, the fly capacitor supplies the charges to the output capacitor via the fourth switch to generate a second output voltage.Type: GrantFiled: September 4, 2008Date of Patent: March 30, 2010Assignee: Novatek Microelectronics Corp.Inventors: Chih-Yuan Hsieh, Chih-Jen Yen
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Patent number: 7688933Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.Type: GrantFiled: January 25, 2007Date of Patent: March 30, 2010Assignee: Casio Computer Co., Ltd.Inventor: Katsuhiko Morosawa
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Patent number: 7688932Abstract: A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.Type: GrantFiled: January 9, 2008Date of Patent: March 30, 2010Assignee: STMicroelectronics SAInventor: Philippe Roquelaure