Abstract: Disclosed herein is a voltage detection circuit including: a voltage detection section; a first voltage determination section; and a second voltage determination section.

Abstract: A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a reverse clock signal input terminal (TSB), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a common node (P), a first switch circuit (31) providing a high level signal to the common node, a second switch circuit (32) providing a low level signal to the common node, a third switch circuit (33) providing a clock signal to the output terminal, a fourth switch circuit (34) providing a low level signal to the output terminal, and an inverter (36) connected between the output terminal and the reverse output terminal.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.

Abstract: An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.

Abstract: A bidirectional shift register in which an operation margin is not lowered when a shift direction of a signal is switched is provided. A unit shift register SRk at one stage of a plurality of stages of shift registers includes a gate line drive unit, a forward shift unit, and backward shift unit each capable of operating as one-stage shift register. The gate line drive unit outputs a gate line drive signal Gk to a gate line GLk in response to a previous-stage forward signal Gnk?1 and a subsequent-stage backward signal Grk+1. The forward shift unit performs only forward shift to output a forward signal Gnk to the subsequent-stage in response to the previous-stage forward signal Gnk?1, and the backward shift unit performs only backward shift to output a backward signal Grk to the previous-stage in response to the subsequent-stage backward signal Grk+1.

Abstract: Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an o

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: A level shift circuit prevents a through current in an output circuit connected to a high-voltage power supply, thereby reducing power consumption and noise and enabling a high-speed operation. The level shift circuit includes first and second bias generating circuits that supply a gate bias voltage to each of a PMOS transistor as a first transistor and a NMOS transistor as a second transistor. Each of the first and second bias voltage generating circuits includes a series connection of a diode-connected PMOS transistor and a diode-connected NMOS transistor. The discharge of a capacitor to the high-voltage power supply is prevented, and a through current is prevented when an output signal transitions from a high-level to a low-level and vice versa, whereby power consumption and noise can be reduced.

Abstract: A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.

Abstract: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.

Abstract: A bandgap voltage reference circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a first diode, a second diode, and a divider. The first transistor, the second transistor, and the third transistor form current mirrors. The reference current of the current mirrors is generated according to the first diode, the second diode, and the first resistor. The reference voltage of the voltage reference circuit is output from the first end of the second resistor. The divider is coupled to the second end of the second resistor so that the reference voltage of the voltage reference circuit can be reduced.

Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.

Abstract: In a current switch, a bias generation circuit electrically connected to a high voltage power supply generates a bias current. The bias current is mirrored by a current mirror containing a first plurality of transistors to a first one of a second plurality of transistors. The first one of the second plurality of transistors amplifies the mirrored bias current and transmits the amplified bias current to a second one of the second plurality of transistors. The second one of the second plurality of transistors sinks the amplified bias current into a node shared by an internal reference voltage, thereby putting the node in a first logic state. A third one of the second plurality of transistors receives the amplified bias current from the second one of the second plurality of transistors and sinks the amplified bias current into a node shared by a gate of a high voltage p-type transistor, thereby putting the node in the first logic state.

Abstract: An object of the present invention is to eliminate fluctuation in the value of the constant current I even if there is characteristic fluctuation in field effect transistors and at the same time, to improve the power consumption.

Abstract: A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

Abstract: This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.

Abstract: A circuit including a voltage-controlled transistor to be switched. A first transistor is switched on, mediated by a control signal, and a first current flows through a series circuit and starts to subject a control input of the voltage-controlled transistor to charge reversal. The first current brings about a first potential shift at a connecting node. A second transistor is switched on by this first potential shift and a second current therefore flows through the switching path of the second transistor into the control input of the first transistor, which amplifies the first current. The increasing charge reversal of the control input of the voltage-controlled transistor brings about a second potential shift at the connecting node, the second transistor is switched off by this second potential shift, and the first transistor remains switched on, however, and holds the voltage-controlled transistor in its new switching state.

Abstract: Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these applications have experienced both decreases in size and increases in speed. As a result, current-mode logic or CML has come into use in some high speed applications, calling for alternative designs for components such as prescalers. Here, a divide-by-three prescaler is described that uses internal states from mater-slave flip-flop pairs and that is well-suited for microelectronics that employ CML.