Abstract: Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.

Abstract: The invention enhances resistance to a surge in a semiconductor device having a semiconductor die mounted on a lead frame. An N type embedded layer, an epitaxial layer and a P type semiconductor layer are disposed on the front surface of a P type semiconductor substrate forming an IC die. A metal thin film is disposed on the back surface of the semiconductor substrate, and a conductive paste containing silver particles and so on is disposed between the metal thin film and a metal island. When a surge is applied to a pad electrode disposed on the front surface of the semiconductor layer, the surge current flowing from the semiconductor layer into the semiconductor substrate runs toward the metal island through the metal thin film.

Abstract: A light-emitting element includes a monolithic understructure including a first surface and a second surface different from the first surface; a plurality of light-emitting structure units disposed on the second surface; and a trench formed on a portion of the first surface and between the plurality of light-emitting structure units, wherein a height of the portion of the first surface is greater than a height of the second surface measured from a bottom of the monolithic understructure, and the portion of the first surface is exposed by the trench.

Abstract: A thin film transistor (TFT) having an active layer pattern, the active layer pattern including a first active layer pattern extending in a first direction; a second active layer pattern extending in the first direction and parallel to the first active layer pattern; and a third active layer pattern connecting a first end of the first active layer pattern to a first end of the second active layer pattern.

Abstract: A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.

Abstract: Disclosed are a thin film transistor substrate and a method of fabricating the same in which the number of processes is reduced. The method includes forming a first conductive pattern including gate electrodes and gate lines on a substrate through a first mask process, depositing a gate insulating film and forming a second conductive pattern including a semiconductor pattern, source and drain electrodes and data lines through a second mask process, depositing first and second passivation films and forming pixel contact holes passing through the first and second passivation films and exposing the drain electrodes through a third mask process, and forming a third conductive pattern including a common electrode and a common line and forming a third passivation film formed in an undercut structure with the common electrode through a fourth mask process, simultaneously, and forming a fourth conductive pattern including pixel electrodes through a lift-off process.

Abstract: A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.

Abstract: Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

Abstract: This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.

Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Abstract: A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.

Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.