Patents Examined by Viktor Simkovic
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Patent number: 6689633Abstract: An optical silicon-based detector with a porous filter layer that has a laterally modifiable filter effect, comprising a plurality of integrated photosensitive cells. The invention also relates to a method for the production of an optical detector by creating an insulating layer on the porous filter layer and by providing active filter surfaces.Type: GrantFiled: September 24, 2001Date of Patent: February 10, 2004Assignee: Forschungszentrum Julich GmbHInventors: Michel Marso, Rüdiger Arens-Fischer, Dirk Hunkel
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Patent number: 6670212Abstract: A method of fabricating a micro-mechanical sensor (101) comprising the steps for forming an insulating layer (6) onto the surface of a first wafer (4) bonding a second wafer (2) to the insulating layer (6), patterning and subsequently etching either the first (4) or second wafer (6) such that channels (18,20) are created in either the first (2) or second (4) wafer terminating adjacent the insulating layer (6) and etching the insulating layer (6) to remove portions of the insulating layer (6) below the etched wafer such that those portions of the etched wafer below a predetermined cross section, suspended portions (22), become substantially freely suspended above the un-etched wafer. This method uses Silicon on Insulator technology. Also disclosed is a micro-mechanical gyroscope structure (101) allowing an anisotropic silicon to be used to fabricate a sensor functioning as if fabricated from isotropic silicon.Type: GrantFiled: July 5, 2001Date of Patent: December 30, 2003Assignee: Qinetiq LimitedInventors: Mark E. McNie, Vishal Nayar
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Patent number: 6664126Abstract: This invention provides a fabrication process for manufacturing of truly 3-dimensional micromechanisms which takes advantages of SOI (silicon-on-insulator) wafers each of which is processed to create a respective structural element of the 3-dimensional micromechanisms by DRIE (deep reactive ion etching) of the wafer and thermal oxidation of the trenches opened during the DRIE etching. The wafers are sequentially bonded into a multistack structure from which the 3-D micromechanism. is released by XeF2 etching. Thermally grown SiO2 is used as structural material for the 3-D micromechanism.Type: GrantFiled: February 27, 2002Date of Patent: December 16, 2003Assignee: University of Maryland, College ParkInventors: Donald Lad Devoe, Lung-Wen Tsai
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Patent number: 6664165Abstract: There is provided a semiconductor apparatus, and a fabrication method thereof, which are improved such that a reduction in concentration at the SOI active layer is prevented, and a parasitic MOSFET is not formed even in cases where Mesa-type isolation techniques and the STI isolation method are applied to form a MOSFET in an SOI layer. In an isolation step for separating and forming a plurality of device regions, a layered film of a nitride film (Si3N4) and an oxide film (SiO2) is taken as an isolation mask, and a semiconductor layer (SOI layer) is removed from the isolation region by etching. Subsequently, a SiON film (7) is formed on a sidewall surface of an SOI layer (3) by a nitridation oxidation process. Thereafter, isolation is performed by the STI method. Finally, an oxide film (9) and an electrode (10) are formed, and a MOSFET is completed.Type: GrantFiled: October 1, 2002Date of Patent: December 16, 2003Assignee: Sony CorporationInventor: Kazuhide Koyama
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Patent number: 6663716Abstract: An apparatus for chemical vapor deposition includes a dispenser for dispensing a precursor to a vaporizer positioned within a vaporization chamber. A delivery conduit joins the vaporization with a process chamber. A flow meter is positioned within the delivery conduit for measuring the flow of precursor through the delivery conduit. A flow controller is likewise positioned within the delivery conduit for controlling the flow of precursor in response to the measured flow rate.Type: GrantFiled: April 14, 1999Date of Patent: December 16, 2003Assignee: CVD Systems, Inc.Inventors: James F. Loan, Jack P. Salerno
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Patent number: 6660537Abstract: A conductive trace is formed over and insulated from a region of semiconductor material, such as a region adjacent to the n+ region of an n+/p− photodiode, and a sawtooth current is made to flow through the conductive trace. The sawtooth current induces charge carriers to move through the semiconductor material to a collection region in the semiconductor material.Type: GrantFiled: August 15, 2002Date of Patent: December 9, 2003Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Philipp Lindorfer, Kyuwoon Hwang
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Patent number: 6660554Abstract: A thermistor having multiple metal layers about at least a portion of a semiconductor body. The thermistor includes a first thick film electrode layer, a reactive metal layer, a barrier metal layer and, optionally, a layer to facilitate attachment to an electrical contact. Also, a method of making the thermistor is described.Type: GrantFiled: December 11, 2001Date of Patent: December 9, 2003Inventor: Gregg J. Lavenuta
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Patent number: 6649442Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.Type: GrantFiled: November 13, 2002Date of Patent: November 18, 2003Assignee: Eastman Kodak CompanyInventor: Eric G. Stevens
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Patent number: 6645790Abstract: The present invention is generally drawn to a system and method for creating RF integrated microwave circuits that can support multiple applications where many RF functions can be derived from a generic integrated circuit after the RF integrated microwave circuit is manufactured. More specifically, the present invention can provide active and passive device building blocks of respective monolithic microwave integrated circuit (MMIC) arrays and substrates that can be coupled together in various ways after manufacture of the integrated circuits to achieve multiple applications. This can accomplished by manufacturing chips with multiple active device blocks that can support various and multiple applications and that can be coupled together in various ways, adjusted, or tuned after manufacture.Type: GrantFiled: December 21, 2001Date of Patent: November 11, 2003Assignee: Anadigics, Inc.Inventors: Sanjay B. Moghe, Carl S. Chun, Pranav N. Patel, Seung-yup Yoo
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Patent number: 6642067Abstract: A method for delicately adjusting an orientation of features in completed micro-machined electromechanical sensor (MEMS) devices after initial formation and installation within the device packaging to trim one or more performance parameters of interest, including modulation, bias and other dynamic behaviors of the MEMS devices.Type: GrantFiled: September 24, 2001Date of Patent: November 4, 2003Assignee: Honeywell International, Inc.Inventor: Paul W. Dwyer
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Patent number: 6638838Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.Type: GrantFiled: October 2, 2000Date of Patent: October 28, 2003Assignee: Motorola, Inc.Inventors: Kurt Eisenbeiser, Barbara M. Foley, Jeffrey M. Finder, Danny L. Thompson
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Patent number: 6638780Abstract: A plurality of LEDs are mounted on a substrate aggregation, a transparent layer is formed on the substrate aggregation. The transparent layer between adjacent divisions is removed to form an individual transparent layer and to form a groove around the individual transparent layer. The groove is filled with a reflector material to form a reflector layer. The reflector layer and the substrate are cut so as to form a reflector film on the outside wall of the individual transparent layer, thereby forming a plurality of LED devices.Type: GrantFiled: June 12, 2002Date of Patent: October 28, 2003Assignee: Citizen Electronics Co., Ltd.Inventors: Koichi Fukasawa, Hirohiko Ishii, Masahide Watanabe
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Patent number: 6635495Abstract: An infrared detecting capacitor formed of a ferroelectric film has its capacitor portion supported by first and second interconnecting lines to be held on an Si substrate located on both sides of a trench. A lower electrode is coupled with the first interconnecting line while an upper electrode is coupled with the second interconnecting line. The capacitor portion is a rectangle in shape in plan view without small triangular sections opposite to each other in the diagonal direction.Type: GrantFiled: May 30, 2001Date of Patent: October 21, 2003Assignees: Matsushita Electric Industrial Co., Ltd., Hochiki Corporation, Murata Manufacturing Co., Ltd.Inventors: Kazuhiko Hashimoto, Tomonori Mukaigawa, Ryuichi Kubo, Hiroyuki Kishihara, Minoru Noda, Masanori Okuyama
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Patent number: 6635506Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.Type: GrantFiled: November 7, 2001Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Richard P. Volant, John C. Bisson, Donna R. Cote, Timothy J. Dalton, Robert A. Groves, Kevin S. Petrarca, Kenneth J. Stein, Seshadri Subbanna
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Patent number: 6630359Abstract: A chemical or biological analysis multi-point micro-system including a structure equipped with micro-wells, each micro-well being intended to receive a reagent coupled with a conductive polymer. Each micro-well includes a reception electrode on which the reagent is fixed by the conductive polymer with which it is coupled. Each micro-well also includes a counter-electrode arranged so as to be able to apply, in a volume of the micro-well, an electric field between its counter-electrode and its reception electrode. The structure further enables the simultaneous connection of all the reception electrodes to a first electric potential and enables the simultaneous connection of all the counter-electrodes to a second electric potential to be able to set up the electric field.Type: GrantFiled: January 31, 2001Date of Patent: October 7, 2003Assignee: Commissariat a l'Energie AtomiqueInventors: Patrice Caillat, Jean-Frédéric Clerc
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Patent number: 6627486Abstract: A method for manufacturing a semiconductor, comprising crystallizing an amorphous silicon film formed on a substrate by employing lateral growth method using a catalyst element which accelerates the crystallization, wherein the duration of annealing accounts for 90% or more but less than 100% of the time for crystallization of the amorphous silicon film under the condition that no catalyst element is used.Type: GrantFiled: October 10, 2000Date of Patent: September 30, 2003Assignee: Semiconductor Energy Laboratory Co. Ltd.Inventors: Hisashi Ohtani, Tamae Takano, Taketomi Asami, Etsuko Fujimoto
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Patent number: 6627518Abstract: A method for making a three-dimensional device is disclosed. The method includes a step of forming a first cleaving layer, a first intermediate layer, and a first transferred layer on a first translucent substrate and forming a second cleaving layer, a second intermediate layer, and a second transferred layer on a second translucent substrate.Type: GrantFiled: October 18, 1999Date of Patent: September 30, 2003Assignee: Seiko Epson CorporationInventors: Satoshi Inoue, Tatsuya Shimoda
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Patent number: 6621539Abstract: A method of manufacturing a reflective type LCD includes the steps of forming one color layer on an approximately overall surface of a display region of a substrate, forming a reflective layer on an approximately overall surface of the one color layer, and partly removing the reflective layer and exposing a pattern of the one color layer through the remaining reflective layer, whereby a reflective type LCD having high display quality can be provided.Type: GrantFiled: April 17, 2001Date of Patent: September 16, 2003Assignee: Alps Electric Co., Ltd.Inventor: Sadao Nakamura
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Patent number: 6620645Abstract: A method for fabricating multi-cell solar devices using thermal spray deposition techniques to spray metal powder directly on solar cells and on the backing upon which solar cells are assembled, to form collection grid lines, bus bars, electrodes and interconnections between solar cells.Type: GrantFiled: November 16, 2001Date of Patent: September 16, 2003Assignee: G.T. Equipment Technologies, IncInventors: Mohan Chandra, Yuepeng Wan, Alleppey V. Hariharan, Jonathan A. Talbott
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Patent number: 6613601Abstract: An ultrananocrystalline diamond (UNCD) element formed in a cantilever configuration is used in a highly sensitive, ultra-small sensor for measuring acceleration, shock, vibration and static pressure over a wide dynamic range. The cantilever UNCD element may be used in combination with a single anode, with measurements made either optically or by capacitance. In another embodiment, the cantilever UNCD element is disposed between two anodes, with DC voltages applied to the two anodes. With a small AC modulated voltage applied to the UNCD cantilever element and because of the symmetry of the applied voltage and the anode-cathode gap distance in the Fowler-Nordheim equation, any change in the anode voltage ratio V1/V2 required to maintain a specified current ratio precisely matches any displacement of the UNCD cantilever element from equilibrium. By measuring changes in the anode voltage ratio required to maintain a specified current ratio, the deflection of the UNCD cantilever can be precisely determined.Type: GrantFiled: May 9, 2002Date of Patent: September 2, 2003Assignee: The University of ChicagoInventors: Alan R. Krauss, Dieter M. Gruen, Michael J. Pellin, Orlando Auciello