Abstract: A microactuator has a first substrate, a second substrate, a first comb electrode having a plurality of first comb elements formed on an inner surface of the first substrate, a second comb electrode having a plurality of second comb elements formed on an inner surface of the second substrate, and a connecting film formed by partially removing an interlayer formed on the inner face of any one of the first substrate and the second substrate. The first substrate and the second substrate face each other with a distance and are movable with respect to each other. The first comb elements and the second comb elements are alternately disposed. Any one of the first electrode and the second electrode is bonded to the connecting film. This microactuator is preferably used in magnetic head units and magnetic recording apparatuses.

Abstract: A semiconductor and a method of manufacturing thereof form a region with a sufficient gettering effect. A p-type channel MOSFET and an n-type channel MOSFET are formed in an n-type semiconductor layer, which is isolated in a form of islands on an SOI substrate. A high-concentration impurity diffused region is formed in such a manner as to surround the p-type channel MOSFET and the n-type channel MOSFET. The high-concentration impurity diffused region has a surface concentration of between 1×1018 atoms/cm−3 and 5×1020 atoms/cm−3 for achieving a desired gettering effect.

Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract: In a method of producing a micromechanical structure for a micro-electromechanical element, a first intermediate layer, which is applied to a first main surface of a first semiconductor wafer, is structured in a first step so as to produce a recess. The first semiconductor wafer is then connected via the first intermediate layer to a second semiconductor wafer in such a way that a hermetically sealed cavity is defined by the recess. Finally, one of the wafers is thinned from a surface facing away from said first intermediate layer so as to produce a diaphragm-like structure on top of the cavity. At least one further intermediate layer is provided between the two semiconductor wavers which, prior to the connection of the two semiconductor wafers, is structured in such a way that the structure formed in said at least one further intermediate layer and the recess in said first intermediate layer define the cavity.

Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Abstract: In a fabrication method of a microstructure array, such as a mold for forming a microlens array, a first insulating mask layer is formed on a conductive portion of s substrate, an array of openings for the microstructure array and at least an opening for an alignment marker are formed in the first insulating mask layer during a common process to expose the conductive portion of the substrate at the openings, and first plated or electrodeposited layers are grown in the openings and on the first insulating mask layer using the conductive portion of the substrate as a cathode. The opening for the alignment marker is surrounded by the array of openings for the microstructure array, and a pattern of the opening for the alignment marker is determined such that a current density distribution at the time of electroplating or electrodeposition can be oppressed.

Abstract: The present invention provides a method for monolithic integration of multiple devices on an optoelectronic substrate. The method, in a preferred embodiment, includes forming an active layer having a given wavelength over a substrate. The method further includes forming an N-type doped layer over a portion of the active layer to form first and second active regions within the active layer, the first active region having the given wavelength and the second active region having an altered wavelength different from the given wavelength. In one exemplary embodiment, the conditions used to form the N-type doped layer, for example, dopant concentration, growth rate and temperature, cause the difference in wavelength between the given wavelength and the altered wavelength.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: A method of forming substrates. The method includes providing a donor substrate; and forming a cleave layer comprising a cleave plane on the donor substrate. The cleave plane extends from a periphery of the donor substrate through a center region of the substrate. The method also includes forming a device layer on the cleave layer. The method also includes selectively introducing a plurality of particles along the periphery of the cleave plane to form a higher concentration region at the periphery and a lower concentration region in the center region. Selected energy is provided to the donor substrate to initiate a cleaving action at the higher concentration region at the periphery of the cleave plane to cleave the device layer at the cleave plane.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: A method for fabricating a thin film transistor (TFT) is provided. The method includes steps of a) providing an insulation substrate, b) forming a conductive layer on the insulation substrate, c) defining the conductive layer as a gate conducting structure by a first photolithography and etch process, d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching the data line layer, the source/drain layer and the junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, and e) heat-treating the junction layer to reduce resistance between the source/drain structure and the channel layer.

Abstract: An implantable substrate sensor has electronic circuitry and electrodes formed on opposite sides of a substrate. A protective coating covers the substrate, effectively hermetically sealing the electronic circuitry under the coating. Exposed areas of the electrodes are selectively left uncovered by the protective coating, thereby allowing such electrodes to be exposed to body tissue and fluids when the sensor is implanted in living tissue. The substrate on which the electronic circuitry and electrodes are formed is the same substrate or “chip” on which an integrated circuit (IC) is formed, which integrated circuit contains the desired electronic circuitry. Such approach eliminates the need for an hermetically sealed lid or cover to cover hybrid electronic circuitry, and allows the sensor to be made much thinner than would otherwise be possible. In one embodiment, two such substrate sensors may be placed back-to-back, with the electrodes facing outward.

Abstract: The present invention is a back illuminated image array device and a method of constructing such a device. The device is generally comprised of an array circuitry layer, a front layer, and a quartz layer. The array circuitry layer is defined on one surface of the front layer. The quartz layer is mounted on the other surface of the front layer. The method of fabricating the device is generally comprised of the following steps. The method provides a wafer having a thick silicon layer, an oxide layer on the thick silicon layer, and a front silicon layer on the oxide layer. The front layer has a first surface and a second surface with the second surface proximal to the oxide layer. Array circuitry is formed on the first surface of the front layer. A temporary layer is applied to the surface of the array circuitry. The thick silicon layer and the oxide layers are removed from the wafer, thereby, exposing the second surface of the front layer. A quartz layer is applied to the second surface.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract: The present invention discloses a method for forming a polycrystalline semiconductor layer on a substrate at an atmospheric pressure, including: providing a chamber having an opening portion and a stage therein; forming an amorphous semiconductor layer on the substrate; positioning the amorphous semiconductor layer formed on the substrate on the stage of the chamber; and irradiating five to twelve laser beam shots to every position of a desired portion of the semiconductor layer over the stage through the opening portion of the chamber.

Abstract: An improved method of imprint lithography involves using direct fluid pressure to press the mold into a substrate-supported film. Advantageously the mold and/or substrate are sufficiently flexible to provide wide area contact under the fluid pressure. Fluid pressing can be accomplished by sealing the mold against the film and disposing the resulting assembly in a pressurized chamber. It can also be accomplished by subjecting the mold to jets of pressurized fluid. The result of this fluid pressing is enhanced resolution and high uniformity over an enlarged area.

Abstract: An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N+ contact region in silicon to permit a good ohmic contact to the silicon for any type device.

Abstract: A semiconductor substrate is coupled to the upper side of a base. After the semiconductor substrate is processed, a lid material is anode-coupled to the semiconductor substrate. For the anode-coupling, first, the semiconductor substrate and the lid material are anode-coupled in a spot pattern. After this, the semiconductor substrate and the lid material are wholly anode-coupled to each other. Thereafter, the laminate including the base, the semiconductor substrate, and the lid material are divided and separated into predetermined individual areas. Thus, a vacuum container having a vacuum cavity formed inside of the laminate including the base layer, the semiconductor layer, and the lid layer can be formed. The vacuum degree of the vacuum cavity of the vacuum container is considerably enhanced compared to that by a conventional process of producing a vacuum container. In addition, scattering of the vacuum degrees of the vacuum cavities can be suppressed.