Abstract: A method for simulating and analyzing two-dimensional current and light distributions of a semiconductor laser including an active layer, a cladding layer, and a light absorbing layer includes obtaining initial values of light distribution and carrier distribution, setting a bias condition, and performing current and light distribution analyses. The calculation of the initial value of the two-dimensional light distribution includes calculating a provisional absorption coefficient of the light absorbing layer from the refractive index of the cladding layer, the refractive index of the light absorbing layer, and the laser light wavelength; obtaining a solution in which the real part of the propagation constant of the wave equation is a maximum, using the provisional absorption coefficient; and repeating the calculation, using a sequential approximation method, until the absorption coefficient in the propagation constant equals the absorption coefficient in the original light absorbing layer.

Abstract: A method for scaling-up an existing and successfully operating telecommunication system to an increased capability telecommunication system by using newer, higher performance components while keeping as much of the original software and hardware architecture as possible. To provide this scaling capability a detailed modeling method is disclosed which allows individual attention to each process of the original software to determine the impact of scaling on key performance parameters such as cycle time. With this method re-use levels of 80-90% of the existing software have been achieved when moving to increased capability telecommunication systems. This re-use means scaled-up systems will have lower development costs and lower risk of software error since a great majority of the software has already been tested and corrected. The model also allows big problems to be discovered and solved in the laboratory instead of at a field installation site where costs will be higher and development more complicated.

Abstract: Systems and methods for determining one or more characteristics of a singular circuit, allowing such circuits to be efficiently designed, tested and manufactured. One of the systems includes: (1) a minimum least-squares ("MLS") determination circuit that receives parameters relating to the singular circuit into a matrix A, determines range and null spaces for the matrix A, applies an orthonormalization procedure to determine a solution x to Ax=b', where b' is an orthogonal projection of a known vector b onto the range space of the matrix A and derives an MLS solution from the solution x and (2) a simulation circuit, coupled to the MLS determination circuit, that employs the MLS solution to simulate an operation of the singular circuit and determine the characteristic therefrom.

Abstract: A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include software emulated digital modules to the hardware modules is provided in RAM circuitry at the message transfer control unit.

Abstract: A delay network of logic circuit delay data composed of a first set of vertices containing first to fourth vertices, and a first set of weighted directional edges containing a first directional edge extending from the first vertex to the fourth vertex, a second directional edge extending from the second vertex to the third vertex, a third directional edge extending from the first vertex to the third vertex, and a fourth directional edge extending from the second vertex to the fourth vertex, is converted into a delay network composed of a second set of vertices containing the first to fourth vertices and an added fifth vertex, and a second set of weighted directional edges containing a fifth directional edge extending from the first vertex to the fifth vertex, a sixth directional edge extending from the second vertex to the fifth vertex, a seventh directional edge extending from the fifth vertex to the third vertex, and an eighth directional edge extending from the fifth vertex to the fourth vertex.

Abstract: A programmable thermal sensor is implemented in an integrated circuit such as a microprocessor. The programmable thermal sensor monitors the temperature of the integrated circuit, and generates an output to indicate that the temperature of the integrated circuit has attained a pre-programmed threshold temperature. In a microprocessor implementation, the microprocessor contains a processor unit, an internal register, microprogram and clock circuitry. The microprogram writes programmable input values, corresponding to threshold temperatures, to the internal register. The programmable thermal sensor reads the programmable input values, and generates an interrupt when the temperature of the microprocessor reaches the threshold temperature. In addition to a programmable thermal sensor, the microprocessor contains a fail safe thermal sensor that halts operation of the microprocessor when the temperature attains a critical temperature.

Abstract: An initial placement of cells, and a routing including wires interconnecting the cells, is provided for a microelectronic integrated circuit. A grid is defined as including a plurality of first gridlines that extend parallel to a first axis, and a plurality of second gridlines that extend parallel to a second axis that is angularly displaced from the first axis. The cells are represented as vertices located at intersections of first and second gridlines, and the wires are represented as edges that extend along the first and second gridlines. Clusters of vertices are created such that each cluster includes vertices located on a respective first gridline. A "cover" is computed as including a minimum block of clusters that are connected to all other clusters by wires extending along the second gridlines. Clusters outside the cover are spatially reordered along the second axis away from the cover in descending order of numbers of wires extending from the clusters along the second gridlines.

Abstract: A simulation based power analysis tool extracts "expected" current waveforms from simulation results. These expected waveforms are then used to represent the power consumption for a corresponding circuit cell or groups of cells from which the waveform is derived. The expected waveform is a statistical representation of a current derived over a number of cycles. The expected waveform is derived by recording the starting time of each power arc with respect to a tool defined clock period. The width of the waveform is derived from the average current, propagation delay and intrinsic delay for arc. The expected waveform can take several forms depending on the accuracy required. Each form has a corresponding memory storage requirement. The starting time for each arc can be stored, which yields the most accurate "true" expected waveform. Alternatively, the minimum, maximum and average starting times for a given power arc can be stored from which a "weighted min-max" expected waveform can be constructed.

Abstract: An emulation device comprising an evaluation microcomputer 100 incorporating a rewritable micro RAM 204, an emulation memory 103 substituting a memory means for a user's program, a supervisor CPU 101 for processing a privileged mode and a control section 102 for controlling the operation of each of the sections, in which the emulation memory 103 provides a microprogram storage region 103A for temporarily storing the microprogram to be transferred to the micro RAM in the evaluation microcomputer 100.

Abstract: A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands, a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed, and an enroller for enrolling new modules into the system by adding further pointers to the table.

Abstract: Method and system for declustering semiconductor defect data in cooperation with wafer scanning tools. Classification codes are assigned to defect data stored in wafer scan records by first determining the local density of the defects within a preselected area of the wafer substrate and by determining the average density of all of the defects on the substrate. A search area is defined around a defect of interest, the search area having a radius proportional to the ratio of the local density to the average density. The defects are marked within the search area, and for each marked defect, a new search area is defined and additional defects are marked. At least one of the marked defects is then assigned with a "cluster" classification code and the remaining defects within the search areas are assigned with a "discardable" classification code.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: Manufacturing yield is increased and cost lowered when a second, substantially identical CPU core is placed on a microprocessor die when the die contains a large cache. The large cache is shared among the two CPU cores. When one CPU core is defective, the large cache memory may be used by the other CPU core. Thus having two complete CPU cores on the die greatly increases the probability that the large cache can be used, and the manufacturing yield is therefore increased. When both CPU cores are functional, the die may be sold as a dual-processor. However, when no dual-processor chips are to be sold, the die are still manufactured as dual-processor die but packaged only as uni-processor chips. With the higher total yield of the dual-CPU die, the dual-CPU die may be packaged solely as uni-processor chips at lower cost than using uni-processor die. An on-chip ROM for generating test vectors, a floating point unit, and a bus-interface unit are also shared along with the large cache.

Abstract: A device for conducting circuit simulation of circuits includes a process calculating unit for calculating device structures of circuit component devices, a device calculating unit for calculating device characteristics based on the device structures, a first circuit calculating unit for calculating first dynamic characteristics of a sample circuit including the circuit component devices based on the device characteristics, a second circuit calculating unit for calculating second dynamic characteristics of the sample circuit based on first parameters and second parameters, and a parameter extracting unit for extracting the first parameters based on the device structures and the device characteristics and for determining the second parameters such that the first dynamic characteristics and the second dynamic characteristics are substantially matched. The second circuit calculating unit conducts the circuit simulation of the circuits based on the first parameters and the second parameters.

Abstract: A tool for providing user-configurable earcons, i.e. auditory cues, includes an earcon event engine responsive to command messages issued by tasks executing on a computer system. The command messages include an index to an earcon data file, which, in turn includes a reference to an audio file and audio parameter data for manipulating the acoustic parameters of the audio wave. A file interpreter provides the audio parameters to an audio processor for generation of the earcon. In one embodiment, the invention can be utilized with MIDI compatible instruments or sound cards.

Abstract: A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.

Abstract: A stochastic simulation method and system are provided. The invention eliminates the need for the use of subroutine calls in a user-written simulation program, and of option flags to direct execution via decision trees, by allowing the user to configure the simulator through choices of options at run-time. The options are presented via a user interface as radio buttons or checkboxes which the user activates. The simulator sets itself up to incorporate only those options. The programmer (that is, the author of software according to the invention) only makes the objects available and ensures that they work together. It is the user who actually configures the simulator. The invention provides a highly extendable structure. By use of inheritance and dynamic allocation of memory, and by design of self-contained objects to represent various components of the simulation system, a simulation program according to the invention incorporates new features and options with a minimum of new code.

Abstract: An air-conditioning and ventilation simulator for predicting environmental conditions in a subsurface space, which includes a first processing portion for obtaining the airflow velocity in branches constituting the subsurface space; a second processing portion for calculating initial values and short-term change values of wall temperature and field temperature in each of the branches, initial values and boundary values of temperature, water-vapor density and carbon dioxide concentration in each of the branches; a third processing portion for calculating the wall temperature, field temperature and airflow temperature in each of the branches; and a fourth processing portion for performing detailed calculation of the airflow velocity, temperature, humidity and carbon dioxide concentration for calculating time-varying data of the airflow temperature, water-vapor density and carbon dioxide concentration in each of the branches by using, as input data, the space structure model data, the airflow analysis result dat

Abstract: An autonomous controller includes a microprocessor, a programmable memory for storing a plurality of cycle structures, a clock/calendar circuit accurate to within a few seconds per month, a lamp driver including a plurality of isolated outputs for operating traffic signals, a display driver for providing a indication of optimum speed through the controlled intersection, and an I/O device coupled between the microprocessor and an external connector for downloading the cycle structures to the programmable memory. The microprocessor reads data from the programmable memory, selects a cycle structure suitable for the time of day, and causes the lamp driver to control the traffic signals in an intersection in accordance with the selected cycle structure.