Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In a computing environment made up of one or more personal computing devices (PCD) and/or one or more powered devices (PD), power source equipment (PSE) determines an allocated amount of power to be supplied to each device. The personal computing devices include a unified LAN-On-Motherboard (LOM) that combines the functionality of a powered device (PD) controller of a conventional PD and a LOM of a conventional personal computing device into a single unified subsystem. This allows the personal computing devices to use the existing hardware architecture and software architecture, such as software drivers and Access Protocol Interfaces (API), with few modifications to implement PoE.

Abstract: A system conducts a plurality of cycles on the powered device. Each cycle has a detection phase and a classification phase. A classification voltage is applied to the conductors during each cycle. The system measures a current in the conductors while the classification voltage is applied. The system determines a final class responsive to a plurality of measured currents. The final class utilized to determine an amount of inline power to deliver to the powered device.

Abstract: A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

Abstract: Methods and apparatuses for the dynamic configuring of profiles used for the control of the frequency of clock signals. At least one embodiment of the present invention provides a means of dynamically generating, storing, updating and using spread spectrum profiles in a clock circuit to provide spread spectrum modulated clock signals and to slew clock frequency.

Abstract: Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

Abstract: Some embodiments of the invention include systems, apparatuses, and methods for dynamically reducing requested supply voltage based on idle functional blocks.

Abstract: A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock.

Abstract: An operating system switching method in a computer system having at least two operating systems is provided. The operating system switching method may include receiving a command of switching a first operating system that is currently running to a second operating system, causing the computer system to make a transition to a low-power sleeping state in response to the command, and booting the computer system using the second operating system in the transitioned state.

Abstract: Taught is a detection device for detecting impacts and the like, comprising an integrated microcontroller (1) which includes an RFID interface (101) and a non-volatile memory (201), the integrated microcontroller (1) being interfaced with at least one suitable sensing means (2) through a suitable digital interface (102), the integrated microcontroller (1) being provided with a power management logic (301) to manage operation modes of the detection device, power consumption of the sensing means (2) being managed by the power management logic (301).

Abstract: For one disclosed embodiment, an apparatus comprises a load circuit having one or more memory devices, one or more temperature sensors to sense one or more temperatures for the load circuit, and supply voltage control circuitry to control supply voltage to be applied to the load circuit. The supply voltage control circuitry may vary the supply voltage based at least in part on one or more sensed temperatures when the load circuit is in an inactive state and may help retain one or more signals by one or more memory devices of the load circuit as the supply voltage is varied. Other embodiments are also disclosed.

Abstract: Systems and methods for processing motion sensor data using various power management modes of an electronic device are provided. Power may be provided to a motion sensor during a first power mode of the device. In response to the motion sensor detecting a motion event with a magnitude exceeding a threshold, the sensor may transmit a wake up signal to a power management unit of the device. In response to receiving the wake up signal, the power management unit may switch the device to a second power mode. The device may provide power to a processor and load the processor with a motion sensing application when switching to the second power mode. During the second power mode, motion sensor data may be processed to determine that the motion event is not associated with an intentional user input and the device may return to the first power mode.

Abstract: Power saving cannot be implemented in the adhoc mode by only the IEEE 802.11 standard. This is because communication partners mutually utilize the power save mode in the adhoc mode, and their states must always be managed. In the adhoc mode, the number of communication partners is not always one, and all stations which join a network are candidates, increasing the load of implementation. To solve this problem, a communication apparatus notifies a change to power save mode by an ATIM packet, RTS packet, or null packet. When the ATIM packet or RTS packet is transmitted, the communication apparatus can notify the partner of a change in mode regardless of whether the partner is in the power save mode. When the null packet is transmitted, the communication apparatus can rapidly notify the partner without waiting for any beacon.

Abstract: A power supplier with combinable power output ports includes plural power output ports which include at least a unit output port, wherein the unit output port has two terminal slots in which two power terminals at different potentials are respectively mounted, and the unit output port can be combined with another power output port to form a combined output port having another voltage output. The power supplier of the present invention, according to the demands of the user, provides different voltage output standards or sets through combining the unit output port with another unit output port or combining the unit output port with the base level output port to transform into the needed voltage output.

Abstract: Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points.

Abstract: A power management system for providing a unified power management of at least one electronic system in a selected environment is provided, wherein the at least one electronic system includes a plurality of electronic components.

Abstract: Disk drive power states are managed. Information is received for use in determining a desired power state of a disk drive that is not currently being accessed. The disk drive is caused to have a spun up power state before the disk drive is next accessed.

Abstract: Novel system and methodology for detecting a Powered Device (PD) in a Power over Ethernet (PoE) system. A PD probing circuit generates a detection signal supplied to the PD and determines a PD response signal produced in response to the detection signal. Based on the PD response signal, the control circuit determines a detection value for identifying the PD. In particular, the control circuit concludes that the PD is a device satisfying a PoE standard if the detection value is in a first predetermined range, and concludes that the PD is a legacy PD device if the detection value is in a second predetermined range outside of the first predetermined range.

Abstract: Embodiments for generating a boost voltage in a computing platform are disclosed.

Abstract: According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program.