Patents Examined by W. Burns
  • Patent number: 4876501
    Abstract: Methods and apparatus for accurately measuring propagation delay through very high speed VLSI devices with a test instrument having errors comparable to the delays being measured. The VLSI device has a plurality of parallel operational signal paths, each with a very short propagation delay. The VLSI device is fabricated with control circuitry for selectively connecting the parallel operational signal paths in series in a test mode so as to define a test signal path comprising multiple operational signal paths. The test signal path has a relatively long propagation delay which can be measured with acceptable accuracy by the test instrument. The test signal path is defined so that it bypasses clocked circuit elements on the VLSI device. Since the operational signal paths are on the same integrated circuit and have very well correlated operating characteristics, the propagation delay through the test signal path is a good representation of the integrated circuit dynamic operation.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: October 24, 1989
    Assignee: Prime Computer, Inc.
    Inventors: Joseph L. Ardini, Brian Lefsky, Barbara J. Farr
  • Patent number: 4873485
    Abstract: Direct voltage measurements of electrical signals are extracted from transmission lines for display in a manner to permit such measurements with picosecond temporal and submicron spatial resolution utilizing a noncontacting electro-optic probe. The probe may have multiple quantum well (MQW) structure. The NQW structure defines an active region sufficiently small (less than a micron if desired) in width so that it can be placed between neighboring lines on an integrated circuit. A short pulse laser beam is used to sense the absorption change at the time window of interest. The electroabsorption effect in the MQW structure is a nonlinear function of the strength of the electric field. Detection can be carried out by sampling techniques to provide the measurement of the voltage or the display of the signal.
    Type: Grant
    Filed: July 13, 1988
    Date of Patent: October 10, 1989
    Assignee: The University of Rochester
    Inventor: Steven L. Williamson
  • Patent number: 4871965
    Abstract: An environmental testing facility for verifying operational conditions of electronic components at predefined temperature extremes is described. A removable multistation holder is configured to have a plurality of components coupled thereto. The multistation holder is coupled to a controllable, rotatable shaft. A hood is placed over the holder, shaft and associated apparatus and placed in contact with a base plate, so that a vacuum can be established in the resulting chamber. A sensing device permits the positioning of the individual components with respect to an interface apparatus. When the component is correctly positioned with respect to the interface apparatus, the interface apparatus is moved to engage the terminals of the components. The electrical signals can be applied to and received from the component through the interface device. After a first temperature condition is established for the multistation holder and consequently for the components coupled thereto, all of the components are tested.
    Type: Grant
    Filed: August 18, 1988
    Date of Patent: October 3, 1989
    Assignee: Apex Microtechnology Corporation
    Inventors: Hubert F. Elbert, Gary March-Force
  • Patent number: 4871963
    Abstract: An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the devices, besides ensuring a higher reliability. The system utilizes special "intelligent" cards, i.e., provided with a card microprocessor which may be connected to a supervisory system's CPU directing the test and classification process of the devices.
    Type: Grant
    Filed: October 17, 1988
    Date of Patent: October 3, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Lucio Cozzi
  • Patent number: 4870347
    Abstract: A universal breakout unit is provided whereby aircraft circuits or systems may be accessed and tested regardless of the design differences between the various aircraft systems. The universal breakout unit comprises an array of associated pairs of input and output jacks which are disposed on a face panel of the breakout unit. Each input jack of each associated pair is uniformly wired to a connection with one or more input connectors. Similarly, each one of the output jacks of the associated pairs is wired to one connection within one or more output connectors. The input and output jacks are selectively coupled to each other through a manual toggle switch. A specially wired harness, corresponding to each specific aircraft circuit, is provided for connection to the input connector or output connector.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: September 26, 1989
    Inventor: Arnold Cicerone
  • Patent number: 4870353
    Abstract: A pre-loaded compression spring assembly is described which preferably includes a compression spring, a base plate to support one end of the spring, and a flexible retention member which extends over the opposite end of the spring and which is adapted to retain the spring in a pre-loaded condition on the base plate. The spring assembly is compressed when force is applied to the upper end of the spring. The spring assembly has a variety of uses, including for example use in circuit board testing apparatus.
    Type: Grant
    Filed: December 30, 1987
    Date of Patent: September 26, 1989
    Assignee: Hewlett-Packard
    Inventor: Stephen J. Cook
  • Patent number: 4870345
    Abstract: A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: September 26, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ichiro Tomioka, Kazuhiro Sakashita, Satoru Kishida, Toshiaki Hanibuchi, Takahiko Arakawa
  • Patent number: 4870356
    Abstract: A universal test fixture for electrically connecting a plurality of component pins to compute test logic without the need for specialized sockets is described. The test fixture comprises a planar dielectric substrate having a multi-conductor pattern on the top surface comprising a plurality of equal width, spaced conductor bars, and including electrical conductors for connecting the spaced conductor bars to test logic. Also provided is a resiliently deformable member or material for compensating for varying planarity between the tips of the component pins to be tested.
    Type: Grant
    Filed: March 8, 1989
    Date of Patent: September 26, 1989
    Assignee: Digital Equipment Corporation
    Inventor: Harvey C. Tingley
  • Patent number: 4870351
    Abstract: An electronic watthour meter employs a first analog signal representing either a load current or voltage to pulse-width-modulate a second analog signal representing the other of the load current or voltage. The resulting signal contains a DC component proportional to the product of current and voltage. AC components are removed from the product signal in an integrator before applying the DC component to a threshold circuit. The threshold circuit alternates its output between positive and negative values each time the DC component of the product signal passes through a predetermined positive and negative value. This pulsed signal is transmitted to a register for integrating the energy usage. A pulse-width modulator produces a constant-frequency pulsed output whose positive and negative alternations have lengths which are proportional to the line signal it receives. At each alternation of the pulsed signal, the output of the pulse-width modulator alternates between a direct and an inverted signal.
    Type: Grant
    Filed: February 7, 1989
    Date of Patent: September 26, 1989
    Assignee: General Electric Company
    Inventor: Miran Milkovic
  • Patent number: 4868493
    Abstract: The invention relates to a device for the functional testing of integrated circuits, in which the integrated circuit to be tested can be connected via adapters to computer-controlled test heads. In order to make the testing device more flexible and increase its efficiency, a test piece (i.e., integrated circuit) with a large number of external terminals can be connected via a special adapter to at least two test heads placed side by side and can be tested by them in common and/or two or more test pieces with a smaller number of terminals can be connected via a second special adapter to a single test head and be tested in common. The invention further relates to associated operating methods.
    Type: Grant
    Filed: September 27, 1988
    Date of Patent: September 19, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Reinhold Becker
  • Patent number: 4862077
    Abstract: A probe card apparatus and method which allows reconfiguration of the probing circuits. A first probe card member has a plurality of incomplete probing circuits which are associated with a plurality of contact holes. An adapter ring member, having a plurality of T-shaped conductive lines terminated in contact holes, is removably mounted in close proximity to the first probe card member. Spring-loaded contact pins provide contact between the members such that the T-shaped conductive lines are used to complete the probing circuit. The T-shaped conductive lines are severable lines, and discrete electronic components can be connected between respective contact holes. As the adapter ring member is of a removably attachable construction, the entire probe card circuitry is reconfigurable by a simple change of the adaptor ring.
    Type: Grant
    Filed: February 13, 1989
    Date of Patent: August 29, 1989
    Assignee: International Business Machines Corporation
    Inventors: Timothy A. Horel, Edward S. Hoyt, Lloyd A. Walls
  • Patent number: 4862069
    Abstract: A circuit tester (12) tests an electronic circuit (10) to determine which of a number of bus devices (16, 18, and 20) on the circuit (10) is stuck in an asserting state and is thus keeping a bus (14) at the asserted voltage level. A back-driving source (21) back-drives the bus (14) to its de-asserted level, and each of the devices (16, 18, and 20) is enabled individually in succession. When a device is enabled, a current meter (22) determines whether the bus current increases as a result. If so, the given device is not the defective device that is keeping the bus asserted. If there is no current change, the device is the defective one. A current limit is imposed on the back-driving source (16). This limit depends on the particular device being enabled; the limit is set higher than the quiescent assertion current on the bus but less than the sum of the quiescent current and the assertion-current capacity of the device being enabled.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: August 29, 1989
    Assignee: GenRad, Inc.
    Inventor: Alan J. Albee
  • Patent number: 4859938
    Abstract: A novel technique to detect oxydonor generation in semiconductor wafers. Oxydonor generation in a P-type substrate may be sufficient to create a P-N junction within the substrate which may adversely affect device performance. A technique of the present invention is a two-step process for determining the presence of such an oxydonor generated P-N junction. For a capacitor device, the capacitance of the device is measured under varying test voltages to determine a capacitance-voltage response. Then a second capacitance-voltage response is measured when the device is subjected to an external energy source. For a diode device, the forward current is measured with the device under varying test voltages to determine a current-voltage response. Then a second currrent-voltage response is measured when the device is subjected to an external energy source. By comparing device response with and without the application of external energy, a device having oxydonor generation problems is efficiently detected.
    Type: Grant
    Filed: July 27, 1987
    Date of Patent: August 22, 1989
    Assignee: Intel Corporation
    Inventors: Sang U. Kim, Mohammad K. Khan
  • Patent number: 4857839
    Abstract: An apparatus for measuring the average characteristics of a semiconductor wafer. The apparatus comprises four electrical contacts removably connected to the wafer at generally equidistant positions on the periphery of the wafer and a flat permanent magnet positioned, adjacent the wafer for applying a substantially uniform magnetic field to one surface of the wafer. The apparatus further comprises control apparatus, connected to each of the electrical contacts for applying current successively to each of four sets of adjacent electrical contacts and measuring the voltage across the opposing set of adjacent electrical contacts in response to each application of current and to each of two sets of opposing electrical contacts and measuring the voltage across the other set of opposing electrical contacts in response to each application of current. As a result, the average dark resistivity, the average dark carrier mobility, and the average dark carrier concentration of the wafer are determined.
    Type: Grant
    Filed: March 2, 1988
    Date of Patent: August 15, 1989
    Assignee: Wright State University
    Inventors: David C. Look, Eileen Pimentel
  • Patent number: 4857838
    Abstract: An apparatus for testing electronic components, on which a testing device can be mounted, provided with a connecting plug for electrical connection of the electrical leads and couplings. Each coupling is provided with a fixed and movable coupling member for mechanical connection, with the couplings securing the testing device in the apparatus in a centered position by the inclined plane method. Stable coupling of the test device to the apparatus is desirable and is achieved by arranging at least three couplings in the form of a star on the appropriate attachment side.
    Type: Grant
    Filed: May 4, 1987
    Date of Patent: August 15, 1989
    Inventor: Hans-Heinrich Willberg
  • Patent number: 4857833
    Abstract: A method of determining which of a plurality of electrical devices connected to a node of a circuit under test is causing a failure at that node by causing individual devices to drive the node one device at a time, taking passive voltage measurements at the node at separate times when individual devices are controlled to drive the node, and analyzing measured voltages resulting when different devices are driving the node to identify which is causing the failure.
    Type: Grant
    Filed: August 27, 1987
    Date of Patent: August 15, 1989
    Assignee: Teradyne, Inc.
    Inventors: Roberto Gonzalez, Lawrence S. Apfelbaum
  • Patent number: 4855673
    Abstract: In an electron beam apparatus in which an electron beam is irradiated on a specimen, secondary electrons are generated from the specimen under the bombardment of the electron beam, and voltage is applied to and a signal voltage is picked up from the specimen through a probe, a metal electrode is disposed on at least part of the outer peripheral surface of the probe through an insulator and the metal electrode is maintained at predetermined electrical potential. The secondary electrons can be shielded from a horizontal electric field generated from the probe and can be detected accurately by means of a detector.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: August 8, 1989
    Assignee: Hitachi, Ltd.
    Inventor: Hideo Todokoro
  • Patent number: 4855672
    Abstract: Disclosed herein is a method and circuit useful in the testing of integrated circuit chips. On-chip test circuitry is provided at a selected location on an IC chip and energized while the chips are still mounted on a lead frame member, wound on reels and heated in an oven. Advantageously, the continuous lead frame member may be a tape automated bond (TAB bond) flexible circuit which is adapted for gang bonding to a large plurality of ICs before being wound on reels. In a preferred test circuit embodiment, the conductive on-off state of digital address circuitry is controlled by applying a test signal potential to an input test pad and through a fuse to a common test circuit junction. This junction is in turn connected between a transistor and diode in a series control network which is operative to control the conductive state of the address circuitry. This network enables the input test pad to be used as both a test signal input connection and a ground connection for the IC test circuit.
    Type: Grant
    Filed: May 18, 1987
    Date of Patent: August 8, 1989
    Inventor: Robert W. Shreeve
  • Patent number: 4855671
    Abstract: Disclosed herein are individual sensor modules for mounting directly upon energized electrical power conductors and systems employing such modules, with principal emphasis upon the provision of both data transmitting and receiving means in each sensor module and at an associated ground station. The modules sense the instantaneous values of all parameters necessary to perform complete metering functions and, in one embodiment, are synchronized by a signal transmitted from the ground station and received by all modules so that the values are measured simultaneously on all conductors at a substation. The signals are transmitted by the modules in a time-synchronized manner and are in a condition for use directly by the ground station microprocessor. In another embodiment, data transmissions by a plurality of modules is synchronized to avoid data collisions by self-contained electronic apparatus within each module, requiring no synchronizing signal from the ground station.
    Type: Grant
    Filed: March 7, 1988
    Date of Patent: August 8, 1989
    Inventor: Roosevelt A. Fernandes
  • Patent number: 4853620
    Abstract: A circuit arrangement for finding a sum of electrical power outputs for use in a multi-phase electricity meter is disclosed. The circuit arrangement comprises a plurality of multiplier circuits arranged in sequence. The sequence of multiplier circuits has two poles which form the output poles of the circuit arrangement. Each multiplier circuit comprises a Hall element, an amplifier, and a polarity reversing switch.
    Type: Grant
    Filed: July 28, 1988
    Date of Patent: August 1, 1989
    Assignee: LGZ Landis & Gyr Zug AG
    Inventors: Mathis Halder, Andreas Joder