Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A method is used for forming an SrTiO3 film on a substrate placed and heated inside a process chamber while supplying a gaseous Ti source material, a gaseous Sr source material, and a gaseous oxidizing agent into the process chamber. Sr(C5(CH3)5)2 is used as the Sr source material. The method performs a plurality of cycles to form the SrTiO3 film. Each cycle sequentially includes supplying the gaseous Ti source material into the process chamber and thereby adsorbing it onto the substrate; supplying the gaseous oxidizing agent into the process chamber and thereby decomposing the Ti source material thus adsorbed and forming a Ti-containing oxide film; supplying the gaseous Sr source material into the process chamber and thereby adsorbing it onto the Ti-containing oxide film; and supplying the gaseous oxidizing agent into the process chamber and thereby decomposing the Sr source material thus adsorbed and forming an Sr-containing oxide film.

Abstract: A method is provided for fabricating a semiconductor device having a gate electrode overlying a gate insulator. The method, in accordance with one embodiment, comprises depositing a layer of spin on glass overlying the gate electrode, the layer of spin on glass comprising a substantially UV opaque material. The layer of spin on glass is heated to a temperature less than about 450° C., and all subsequent process steps in the fabrication of the device are limited to temperatures less than about 450° C.

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

Abstract: Reactors and methods for miniaturized reactions having enhanced reaction kinetics. In particular the subject matter is directed to chemical and biological reactions conducted in a nanoporous membrane environment. The subject matter contemplates methods for modifying the kinetics of reactions and devices for conducting reactions having modified kinetics. The subject matter also provides systems for rapid miniaturized reactions. Further the subject matter includes methods and kits for conducting a reaction with enhanced throughput and methods of conducting miniaturized, high throughput analyses of reaction products, and the like. Reactions performed on or within a nanoporous membrane exhibits improved kinetic characteristics.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate including a pattern for forming a multi-plane channel, forming a columnar polysilicon layer over the insulation layer and filling in the pattern, and performing a thermal treatment process.

Abstract: Methods and systems for in situ process control, monitoring, optimization and fabrication of devices and components on semiconductor and related material substrates includes a light illumination system and electrical probe circuitry. The light illumination system may include a light source and detectors to measure optical properties of the in situ substrate while the electrical probe circuitry causes one or more process steps due to applied levels of voltage or current signals. The electrical probe circuitry may measure changes in electrical properties of the substrate due to the light illumination, the applied voltages and/or currents or other processes. The in situ process may be controlled on the basis of the optical and electrical measurements.

Abstract: In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained.

Abstract: Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film and a second film disposed on at least one side of or inside of the first film, and includes a plurality of nano particles arranged substantially in parallel to each other. In addition, provided are a method of manufacturing a nano semiconductor sheet and methods of manufacturing a TFT and a flat panel display using the nano semiconductor sheet. The method of manufacturing a nano semiconductor sheet, includes: forming first polymer micro-fibers having a plurality of nano particles arranged substantially in parallel; preparing a first film; and arranging a plurality of the first micro-fibers on at least one side of or inside of the first film.

Abstract: A supporting substrate is laminated on a wafer in such a manner that the supporting substrate locked in peripheral edges with a plurality of locking claws is disposed in proximity to and facing to an adhering surface of a double-sided adhesive sheet on the workpiece, the supporting substrate is pressed by a pressing member made of an approximately hemispherical elastic body from an approximate center of a non-adhering surface of this supporting substrate, the supporting substrate is laminated by elastically deforming this pressing member on the wafer while making the supporting substrate surface contact in a flat condition.

Abstract: The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.

Abstract: A method produces a semiconductor device having an interconnection structure disposed above a substrate, wherein the interconnection structure has an interconnection and an insulator layer including a low-permittivity layer. The method includes an etching step forming openings in the insulator layer to expose a surface of the interconnection by dry etching, a cleaning step cleaning the surface of the interconnection and the openings in the insulator layer, and a forming step forming another interconnection by filling a conductor material into the openings. The cleaning step includes a first cleaning process using a cleaning liquid, a rinsing process using a rinsing liquid including water and carbonic acid or organic acid, and a second cleaning process using a neutral or alkaline hydrogen aqueous solution that is supplied to the surface of the interconnection and the openings in the insulator layer.

Abstract: Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Abstract: To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.

Abstract: Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction.

Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.

Abstract: A polysilicon thin film transistor (TFT) may include a substrate, at least one insulating layer, a semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a heat retaining layer formed to contact the semiconductor layer. The heat retaining layer may reduce and/or prevent a reduction in a melt duration time of amorphous silicon during a crystallization process for forming a polysilicon layer of the TFT.