Abstract: An apparatus for heating a chip includes: a laser generator for emitting a laser beam to a semiconductor chip to heat the semiconductor chip; and a beam intensity adjuster disposed on a laser emission path between the semiconductor chip and the laser generator to equalize the intensity of the laser beam to be emitted to the semiconductor chip. A flip chip bonder having the chip heating apparatus, and a method for bonding a flip chip using the same are also provided.

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: A multi-wavelength white light-emitting structure uses a UV light emitting diode chip and a blue light emitting diode chip to excite a red phosphor and a green phosphor and generates a white light-emitting structure having good color rendering. The multi-wavelength white light-emitting structure uses a UV light emitting diode chip that emits light having a wavelength of between 350˜430 nm to excite a red phosphor to emit red light having a wavelength of between 600˜700 nm. The present invention then uses a blue light emitting diode chip that emits light having a wavelength between of 400˜500 nm to emit blue light and uses the blue light emitting diode chip to excite a green phosphor to emit green light having a wavelength of between 490˜560 nm. Mixing the red light, the blue light and the green light forms a white light.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard mask film pattern; forming a barrier film on the semiconductor substrate including the first trenches; forming an ion implantation mask film for exposing the first trenches on the barrier film; forming an ion implantation region in the semiconductor substrate below the first trenches using the ion implantation mask film and the barrier film; forming bulb-shaped second trenches by a second etching process using the ion implantation mask film and the barrier film as a mask, so that bulb-type trenches for recess channels, each including the first trench and the second trench, are formed; and removing the ion implantation mask film and the barrier film.

Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

Abstract: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced.

Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.

Abstract: The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.

Abstract: An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.

Abstract: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to detect the variable capacitance.

Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.

Abstract: A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a second conduction type MOS transistor having a gate electrode provided in a second trench formed in the insulation film, the first conduction type and the second conduction type being opposite types.

Abstract: A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

Abstract: A III-V group nitride system semiconductor self-standing substrate has: a first III-V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a second III-V group nitride system semiconductor crystal layer that is formed up to 10 ?m from the surface of the substrate on the first III-V group nitride system semiconductor crystal layer and that has a dislocation density distribution that is substantially uniform.

Abstract: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to a wet etching process.

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.