Abstract: a semiconductor die having bump type contact areas thereon with film strip leads bonded thereto and fired glass encapsulating only the active side of the die and the bump contact areas. The method of encapsulation includes bonding the film strip leads to the bumps of the die, coating the bumps and active area with unfired glass and firing the glass at a temperature generally below 450.degree. C. The method also includes bonding the film strip leads to the bumps and firing the glass simultaneously or firing the glass and remelting glass covering the bumps to bond the leads to the bumps through the fired glass.

Abstract: An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface.

Abstract: An efficient electron emitter cold cathode is formed by first placing an ype monocrystalline substrate of about 100 to about 500 microns in thickness in a furnace. The furnace is heated to about 850.degree. C. to about 900.degree. C. and an N-type layer of about 10 to 15 microns of SnO.sub.2 is deposited onto the top surface of the substrate using a suitable carrier gas. Then, a P-type layer of about 10 microns of SnO.sub.2 is deposited on the N-type layer. The furnace is then cooled at a rate of about 10.degree. C. per minute to about 600.degree. C. to form the emitter. The furnace is then cooled to room temperature and the emitter removed from the furnace. The emitter is subjected to etching and polishing to obtain a P-type layer of about 2 to 4 microns, and a nonreactive metal contact is then deposited on the P-type layer. The emitter is then completed by bonding a metal contact to the base of the N-type monocrystalline substrate.

Abstract: A method is provided for producing a fast response, insulated junction thermocouple having a uniform diameter outer sheath in the region of the measuring junction. One step is added to the usual thermocouple fabrication process that consists in expanding the thermocouple sheath following the insulation removal step. This makes it possible to swage the sheath back to the original diameter and compact the insulation to the desired high density in the final fabrication step.

Abstract: Lithographic offset alignment techniques for MOS dynamic RAM memory cell fabrication to enable increased packing density while maintaining the minimum patterned geometry. Technique of cell fabrication involves initial oxidation of P-type silicon, for example, followed by silicon nitride deposition. Thereafter, moats are etched using the composite silicon dioxide-silicon nitride layers, followed by boron deposition or ion implantation in regions of the silicon substrate exposed by the etching treatment. The moats are then filled by oxidation to form a large field deposit of silicon dioxide extending above the level of the oxide layer in the regions where the moats were formed. The remaining composite silicon dioxide-silicon nitride layers are then removed, followed by gate oxidation. A P-type ion implant is provided beneath the thin oxide region between the regions to be overlaid by a polysilicon electrode and the thick field oxide of the succeeding cell.

Abstract: A method of fabricating gallium arsenide MOS devices with improved stoichiometric and electrical properties is disclosed. The device includes a gallium arsenide substrate overlaid with a native oxide and an aluminum oxide layer. The device is fabricated using a plasma oxidizing process.

Abstract: A method and resulting structure for a relative humidity monitor which can be built into an integrated circuit chip. A small area on a silicon chip is made porous by anodic etching. This region is then oxidized and a metal counter electrode is deposited over part of the porous area. The surface area in the dielectric under the counter electrode is very high and because of the openness of the structure, ambient moisture can quickly diffuse into the dielectric under the electrode and adsorb onto the silicon dioxide surface. Changes in ambient humidity will then be reflected by measurable changes in capacitance or conductance of the device.

Abstract: A method of manufacturing an indicating element comprises forming an electrode on a rear surface of a semiconductor base plate, forming an N-type or P-type planar indicating layer on an upper surface of the base plate by means of diffusion or crystal growth, and mounting on the planar indicating layer the electrode layer having a desired pattern thereon.

Abstract: A method of fabricating highly miniaturized semiconductor devices which must be electrically but not thermally insulated from ground, by replacing the conventional disk of beryllium oxide with a portion of the substrate itself so as to decrease the thermal resistance. To this end one starts with a disk of "PIN"-structure silicon. On one of its faces (P or N as the case may be) one deposits by epitaxy, or forms by successive diffusions, the active layers of the device and the surdoped zones. The "PIN" diode may be reverse biased if it is desired to create a capacity between active layers and metallic support serving as heat sink. Diodes and transistors in high-frequency microelectronics obtained by the method are also described.

Abstract: An insulated gate field effect transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter.

Abstract: A hybrid mosaic IR/CCD focal plane structure is fabricated using planar thin film interconnects. Rows of detectors are formed on an integrated circuit substrate so that the rows of detectors are adjacent to rows of electrical contacts on the integrated circuit. Contact pads are plated onto the rows of contacts and the regions between adjacent rows of detectors are backfilled with an insulating material. The insulating material is then lapped to expose the contact pads and to form an essentially coplanar surface with the detectors. Thin film interconnects are formed over the coplanar surface between the exposed contact pads and detectors in the adjacent row.

Abstract: In one embodiment, a relatively thin layer of polysilicon is deposited on an underlying region to which spaced-apart electrical contacts are to be made through a subsequently formed relatively thick insulating layer. The polysilicon is selectively masked by a patterned silicon nitride layer in the regions where contact windows are to be formed. The unmasked polysilicon is then converted to a relatively thick insulating layer in an oxidizing step. Thereafter the silicon nitride portions are removed and the remaining polysilicon is utilized to provide conductive regions in the defined windows. In another embodiment, a relatively thick layer of polysilicon is selectively masked and partially converted to silicon dioxide to define both the insulating layer and the conductive regions. In still another embodiment, a relatively thin layer of polysilicon is patterned and then entirely converted to silicon dioxide to form an insulating layer having windows defined therein.

Abstract: A method of producing semiconductor devices having high reverse blocking ability comprising initially forming grooves in at least one major surface of a semiconductor disc of a first conductivity type according to a pattern which subdivides the disc into areal sections capable of being separated into individual device-containing semiconductor wafers and then subjecting the disc to a diffusion process to provide in each section a sequence of layer type zones of different conductivities which form at least one pn-junction and with one of the layer zones being a highly resistive zone, and to provide a zone of single conductivity type passing through the entire disc in the profile region of each of the grooves. A recess is then formed in each section of the major surface which is adjacent the pn-junction which is to be stressed in the reverse direction during use of the intended device and adjacent to each of the grooves.

Abstract: An integrated circuit aluminum-silicon electrical contact may be fabricated in a diffusion region formed in a monocrystalline silicon semiconductor layer by converting the upper portion of the diffusion region into an amorphous region. Alloy pitting is substantially decreased since the solubility of silicon in aluminum is highly dependent upon crystallographic orientation of the silicon and decreases as the silicon approaches an amorphous form. The amorphous region may be formed by implanting arsenic ions with an energy of at least 180 keV and a dosage of approximately 10.sup.15 ions/cm.sup.2.

Abstract: A heterojunction or Schottky barrier photovoltaic device comprising a conductive base metal layer compatible with and coating predominately the exposed surface of the p-type substrate of the device such that a back surface field region is formed at the interface between the device and the base metal layer, a transparent, conductive mixed metal oxide layer in integral contact with the n-type layer of the heterojunction or Schottky barrier device having a metal alloy grid network of the same metal elements of the oxide constituents of the mixed metal oxide layer embedded in the mixed metal oxide layer, an insulating layer which prevents electrical contact between the conductive metal base layer and the transparent, conductive metal oxide layer, and a metal contact means covering the insulating layer and in intimate contact with the metal grid network embedded in the transparent, conductive oxide layer for conducting electrons generated by the photovoltaic process from the device.

Abstract: A method of manufacturing charge transfer devices in which an asymmetrical potential well in the direction of charge transfer is formed by the shape of narrower portions of a transfer channel which is bordered by highly doped channel stoppers. Impurities are diffused through a first mask into a polycrystalline silicon layer on the surface of a semiconductor substrate to construct transfer electrodes of highly doped polycrystalline layer. Then impurities are diffused into a semiconductor substrate through openings bordering on one edge with a first mask to form the highly doped portions to make the narrower portions of the transfer channel to assure that the edges of the transfer electrode and the edge of the narrower portion are aligned.

Abstract: A semiconductor solar cell capable of converting incident radiation to electrical energy at high efficiency includes a plurality of series-connected unit solar cells formed on a common wafer of semiconductor material. The unit solar cells each include a semiconductor substrate of one conductivity type and a p-n junction formed in the substrate. The light-receiving surface of the cell may have an opaque member thereon, and incident light may be directed onto the portion of that surface not covered by the opaque member. Various embodiments and methods illustrate the invention.

Abstract: This relates to a semiconductor device and method for making same. At least one semiconductor device is formed in a polished silicon slice, and the device is framed by a deep diffusion of boron. The surface of the slice is then coated with a layer of silicon nitride, and a glass ceramic body is bonded to the silicon nitride layer. The device is next isolated by isotropic etching, and the silicon from beneath the device is removed with a selective etch so that metal interconnections can be made to the underside of the device.

Abstract: A method for manufacturing ROM's composed of a plurality of matrix-arranged IGFET's comprises a process for manufacturing a semiconductor device with no information yet written therein and a process for completing the ROM by writing predetermined information or memory in the no-information semiconductor device according to orders from users.

Abstract: Described is a method of fabricating front-illuminated silicon photodiodes having high quantum efficiency, a short response time, (high gain and low excess noise in the case of avalanche diodes), low dark currents and good reliability. In the fabrication of an n.sup.+ -p-.pi.-p.sup.+ APD the method includes the steps of: (1) epitaxially growing a high resistivity .pi.-type silicon layer on a high conductivity p-type silicon substrate; (2) forming an n-type guard ring in the .pi.-layer; (3) forming a p-type channel stop around the guard ring; (4) forming in the .pi.-layer a p-layer by ion implantation and by driving in the implanted ions by heating in a suitable atmosphere; (5) masking the p-layer and introducing phosphorus into the backside to getter defects and/or impurities; (6) ramping the furnace temperature during steps (2) through (5) to reduce crystalline defects; (7) forming a thin n.sup.+ -layer in the p-layer; (8) forming an anti-reflection and passivation coating on the n.sup.