Abstract: In an interrupt-driven data frame stream receiver, an interrupt to a host processor is applied by an interrupt system that comprises a timer logic circuit, an address match circuit, a data frame counter, a cyclic redundancy check (CRC) logic circuit, a frame length logic circuit, and a frame content detector. Each of these circuits is coupled to an OR gate. A Start Frame Delimiter (SFD) detector is connected to the inputs of the other circuits.

Abstract: Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.

Abstract: A method for providing rapid recovery from a network file server failure through the use of a backup computer system. The backup computer system runs a special mass storage access program that communicates with a mass storage emulator program on the network file server, making the disks (or other mass storage devices) on the backup computer system appear like they were disks on the file server computer. By mirroring data by writing to both the mass storage of the file server and through the mass storage emulator and mass storage access program to the disks on the backup computer, a copy of the data on the file server computer is made. Optionally, selected portions of the data read through the mass storage emulator program can be altered before being returned as the result of the read operation on the file server. In the event of failure of the file server computer, the backup computer can replace the file server, using the copy of the file server's data stored on its disks.

Abstract: A sequence operation processor and a sequence operation processing method for processing sequence operations at high speed using a multi-port RAM. The sequence operation processor reads data from the multi-port RAM and performs operations as instructed. An operation result which is to be written into RAM is stored in a data register and in a desired address of the multi-port RAM. If the next sequence operation requires that a different address in the multi-port RAM be read, the sequence operation processor writes the operation result to the previously desired address and simultaneously reads the data corresponding to the designated address of the next sequence operation.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

Abstract: A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of the following operations: a left or right shift of bits of the word; and rotation (to the left or right) of bits of the word. In a preferred implementation, the circuit includes a set of multiplexer stages and circuitry for selectively inverting the order of the bits of the word input to, and the word output from, the set of multiplexer stages. Each of the multiplexer stages shifts the bits of the word it receives either by zero bits (in response to a first control signal), or by a positive number of bits (in response to a second control signal). By selectively controlling various subsets of the multiplexer stages, the bits of the input word can be shifted by any of a number of places (from zero to N, where N is some positive number).

Abstract: A mechanism for efficiently overlapping multiple operand types is used in a microprocessor which includes a plurality of execution units and a mechanism to provide operations, which include one or more operands, to the plurality of execution units. Each of the plurality of execution units interprets the one or more operands as different types of operands, and the mechanism to provide operations overlaps the different types of operands.

Abstract: An integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to a bus on which one or more host adapters are connected so that both the host adapters and a host computer can transfer data to and from the circuit, and supply addresses to control operation of this data function circuit. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that includes a data port, a memory address port, and a memory control port. A buffer memory is connected to the buffer memory port. A data function circuit in the buffer memory controller is coupled to a data function enable output line.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

Abstract: An information processing apparatus has a processing unit exclusively used for code information and a processing unit exclusively used for pattern information so that a total processing speed and a processing efficiency is increased when both the code information and the pattern information are processed by the same information processing apparatus. A code information processing unit exclusively processes the code information. A pattern information processing unit exclusively processes the pattern information, the pattern information processing unit being separated from the code information processing unit. Inputting/outputting information to/from each of the code information processing unit and pattern information processing unit is controlled so that a suitable processing can be applied to each of the code information requiring a relatively small processing capability and the pattern information requiring a relatively large processing capability.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift and rotate circuit, a 2-bit shift and rotate circuit and a 4-bit shift and rotate circuit. For double word sized (32-bit) operands, the variously sized shift and rotate circuits may be selectively enabled to perform between 1-bit and 31-bit shift/rotate/pass operations. For byte sized operands, the 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range, i.e., 1-bit to 7-bit, of possible shift/rotate operations.

Abstract: An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Abstract: A remotely-configurable information distribution system selectively filters inbound information in response to selection and limit parameters provided by a remotely-connected processing device. The selection and limit parameters are assembled as a data packet at the device and the packet is uploaded to the host computer over a limited-bandwidth, communications network. Remote software modules resident in the device facilitate both entry of the parameters by an authorized user and the subsequent transfer of those parameters to the host computer. A communications system of the host computer receives the data packet and transfers the packet to a host-based "filtering" software subsystem, where selected portions of the inbound information are extracted in response to the parameters of the data packet. Upon completion of this latter process, the extracted information is transferred is to the remote processing device over the network in accordance with a non-interactive, asynchronous transfer protocol.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A method and system for connecting to, browsing, and accessing computer network resources are provided. In a network in which the preferred embodiment of the present invention operates, a client video display includes a container called "Network Neighborhood." The Network Neighborhood provides a constrained view of the network in a NOS-independent manner. The Network Neighborhood provides a constrained view of the network by displaying only those network resources that are determined to be interesting to the user. Further, the Network Neighborhood provides this view in a NOS-independent manner by displaying all of the network resources in a consistent manner, regardless of the type of client software that was used to enumerate or discover the network resources. In the preferred embodiment of the present invention, each type of client software installed on a client determines a list of network resources that are interesting to the user.