Abstract: A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.

Abstract: A peripheral card having a Personal Computer ("PC") card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash "floppy" is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

Abstract: A system capable of granting Internet access to users when direct connection to their usual home Internet Service Providers (ISPs) is impossible, impractical or prohibitively expensive. The system offers users a unified method of login to other independent ISPs to provide easy and inexpensive access to the Internet and its various services. The system validates user logins, generates billing data, provides usage time and monitors communication links. The system also isolates the shells of the servers of the ISPs from the user until such time as the user has been determined to be valid, thereby providing security to the ISPs against unauthorized access to their servers. The system performs these tasks while requiring only a small amount of communication bandwidth for communication monitoring and billing.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A system and method for controlling a slave processor from a master processor in which the slave processor is instructed to await the occurrence of a particular event and the arrival of a number of data words before processing additional requests. A wait request from the master processor includes identification of an event which must occur before processing is to resume. The master processor provides a number to a register accessible to the slave processor to indicate how many data words to await. The slave processor discontinues processing upon receiving the wait request. The slave processor detects the occurrence of the event and the arrival of the data words and then resumes processing. The register may include an indicator or flag that indicates when the number of data words set by the master processor has been received.

Abstract: The invention relates to exchangeable memory or PC-cards with several integrated circuits for personal computers. These PC-cards are used as a large capacity mass memory for replacing floppy disks and other exchangeable magnetic supports. To protect the content of these PC-cards against unauthorized use, the invention proposes the incorporation into the card (CC) of a specific security integrated circuit chip (MPS), which performs a clearance function for access to the memory chips (MEM). A microcontroller (MPC) also placed in the card comnunicates with the computer and with the security circuit. It makes the security chip validate a confidential code introduced from the computer, whilst also supplying memory chip control signals as a function of the validation result.

Abstract: A computer device for receiving and utilizing a radio card. The radio transceiver is self contained inside the radio card and has antenna contacts disposed on the radio card on one end and an electrical interface on the other. The computer device receives the radio card such that it engages the electrical interface. The computer device additionally has and cap which covers the opening into which the radio has been inserted. Antenna contacts are disposed on the cap to engage the antenna contacts on the radio card. At least one antenna is operably connected to the radio card through the cap. A band is used to attach the cap to the housing of the computer device. The antenna or antennas are embedded in the cap, in the band, or embedded in or attached to the housing of the computer device. Positioning two similar antennas in different position creates an antenna diversity scheme. Shielding can be added to the cap to help reduce the escape of electronic noise.

Abstract: A one-chip CPU (Central Processing Unit) includes a program counter, a built-in inside memory, a gate circuit, a decode circuit, and an inside bus. The program counter is connected to the inside bus and built-in memory while the memory is connected to the decode circuit via the gate circuit. Further, the program counter is connected to the gate circuit. When the logical value of the program counter is representative of the built-in memory, an inhibit signal is not fed to the gate circuit. However, when the logical level is representative of an outside memory, the inhibit signal is fed to the gate circuit so as to close it. As a result, the gate circuit obstructs the flow of data from the built-in memory. This protects data stored in the built-in memory from illicit access.

Abstract: A transceiver as provided for effectively multiplexing IDE address and data lines with selected ISA address and data lines. Compatibility among the IDE data transfers and ISA functions are achieved by multiplexing the ISA lines that do not involve the ISA refresh of the ISA expanded memory. The transceiver includes an enable input that, when disabled, effectively isolates the IDE data lines from the ISA bus so that IDE data transfers can occur. When the enable input is active, the ISA lines not related to refresh are connected to the IDE data lines so that ISA operations can occur. Furthermore, a directional input is included in the transceiver for allowing a central processing unit to control the ISA when the directional input is active and for allowing a PCI/ISA bridge between the PCI bus and the ISA bus to control the ISA operations included the multiplexing. The result is a rearrangement of the IDE data lines with the ISA bus to eliminate a multitude of pins and connectors.

Abstract: A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles used to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. This level of capability is provided by only information in the I/O command blocks within the chain. A method for specifying concurrent execution of a string of I/O command blocks stored in a memory using only information in the string of I/O command blocks allows concurrent execution of a plurality of I/O commands. The method first configures one I/O command block in the string as a head of string concurrent I/O command block. Another I/O command block in the string is configured as an end of string concurrent I/O command block. The remaining I/O command blocks, i.e.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: An extensible central processing unit (CPU) (12 or 12'). By modifying the architecture of a new or prior art CPU, a new or prior art CPU can be made extensible so that new instructions can be added in a simple and cost effective manner to meet differing customer needs. The term "extensible" in regard to a CPU is used to mean that new instructions can be added to the CPU simply by adding certain designated circuitry, without the need to significantly change the existing CPU circuitry. In some embodiments, the additional designated circuitry may include control circuitry in the form of CPU control extension circuitry (52 or 152). In some embodiments, the additional circuitry may include non-control circuitry in the form of execution unit extension circuitry (153).

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A circuit to control a network interface includes a first interface circuit and a second interface circuit. The first interface circuit is capable of negotiating one protocol to use from a plurality of known interface protocols. The first interface circuit controls the network interface when the negotiated interface protocol is supported by the first interface circuit. Otherwise, if the second interface circuit supports the negotiated protocol, the first interface circuit releases control of the network interface to the second interface circuit. The first interface circuit takes control of the network interface from the second interface circuit when the second interface circuit signals the first interface circuit that reliable communication with the network has been lost.

Abstract: In the processing and transmission of an image, there is generated additional information relative to the transmitting apparatus or to the image signal to be transmitted, then an image signal representing an input binary image and an iamge relative to the additional information is binary encoded, or an input multi-value image signal is multi-value encoded, and the binary encoded image signal and the multi-value encoded image signal added with data relative to the additional information are selectively released.

Abstract: A structural key is checked under program control to control the mode of operation for a processor-based electronic circuit board. A break-away key portion of the circuit board is connected to the main portion along a boundary of frangible links with circuit paths traversing the boundary and carrying logic signals. The presence or absence of the break-away portion is sensed by sensing the bit pattern at an I/O address. If the absence of the break-away portion is sensed, the function of a user-commanded motion block is tested and processor operation is limited to executing functions for the mode corresponding to the absence of the break-away portion.

Abstract: In a parallel data processing control system for a parallel computer system having a plurality of computers and an adapter device connecting the computers to each other, a first unit, which is provided in the adapter device, transfers pieces of data processing progress state information to the computers. The pieces of the data processing progress state information respectively indicate data processing progress states of the computers. A second unit, which is provided in each of the computers, holds the pieces of the data processing progress state information. A third unit, which is provided in each of the computers, holds management information indicating a group of computers which share a data process. A fourth unit, which is provided in each of the computers, determines whether or not the computers in the group have completed the data process on the basis of the pieces of the data processing progress state information and the management information.

Abstract: A computer system having a scaleable software architecture is disclosed. The scaleable communication or data replication architecture that enables transparent replication of data or state information over a network of geographically dispersed processing units. Transparent data replication over a geographically dispersed computer network is useful in applications such as parallel computing and disaster recovery. The communication architecture also provides a transparent interface to a kernel I/O subsystem, device drivers and system applications. The communication architecture provides a distributed data model presenting a single system image of the I/O subsystem that allows two or more geographically dispersed processing units or clusters thereof, access to common data. In one particular implementation, the communication architecture permits RAID algorithms, such as RAID level 1 and RAID level 5 state information to be applied to the geographically dispersed network for site disaster recovery.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.