Abstract: A display device may include a pixel disposed in a display area. The pixel may include first and second electrodes; a light emitting element disposed between the first and second electrodes; a first insulating pattern disposed on the light emitting element such that first and second ends of the light emitting element are exposed; a second insulating pattern disposed on the first insulating pattern such that ends of the first insulating pattern are exposed; a third insulating pattern disposed on the second insulating pattern and overlapping ends of the second insulating pattern; a first contact electrode disposed on the first end of the light emitting element, and electrically connecting the first end of the light emitting element to the first electrode; and a second contact electrode disposed on the second end of the light emitting element and electrically connecting the second end to the second electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body.

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

Abstract: A light emitting device may include first electrodes and second electrodes that are spaced apart from each other in a first direction, light emitting elements electrically connected between adjacent first and second electrodes among the first and the second electrodes, and a third electrode spaced apart from the first electrodes and the second electrodes. The third electrode may be electrically separated from the first electrodes and the second electrodes.

Abstract: A fabric-based item may include fabric layers and other layers of material. An array of electrical components may be mounted in the fabric-based item. The electrical components may be mounted to a support structure such as a flexible printed circuit. The flexible printed circuit may have a mesh shape formed from an array of openings. Serpentine flexible printed circuit segments may extend between the openings. The electrical components may be light-emitting diodes or other electrical devices. Polymer with light-scattering particles or other materials may cover the electrical components. The flexible printed circuit may be laminated between fabric layers or other layers of material in the fabric-based item.

Abstract: The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element.

Abstract: An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.

Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.

Abstract: A capacitor includes a silicon substrate, a conductor layer, and a dielectric layer. The silicon substrate has a principal surface including a capacitance generation region and a non-capacitance generation region. The silicon substrate includes a porous part provided in a thickness direction in the capacitance generation region. The conductor layer includes a surface layer part at least covering part of a surface of the capacitance generation region and a filling part filled in at least part of the porous part. The dielectric layer is provided between an inner surface of the porous part and the filling part. The porous part includes a macroporous part having macro pores and a nanoporous part formed in at least part of inner surfaces of the macro pores and having nano pores smaller than the macro pores.

Abstract: A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: A mixed light light-emitting diode device includes first, second, and third chips, each having a first-type semiconductor layer with a first surface, a second-type semiconductor layer with a second surface opposite to the first surface, and a third surface indenting from the first surface and situated on the second-type semiconductor layer. The second and third chips have their first surfaces disposed above and facing the first surface of the first chip. A first-type electrode penetrates through the second and first surfaces of the first chip and contacts all first surfaces of first, second, and third chips. Two second-type electrodes each penetrates through the second and third surfaces of the first chip and connect the first chip to one of the second and third chips.

Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Abstract: An exemplary method of manufacturing a white light emitting device may include providing first LEDs and second LEDs operable to generate excitation light having a dominant wavelength in a range from 440 nm to 480 nm; providing a first photoluminescence material which generates light having a peak emission wavelength in a range from 500 nm to 590 nm; providing a second photoluminescence material which generates light having a peak emission wavelength in a range from 600 nm to 650 nm; disposing the second photoluminescence material over and into direct contact with the second LED; and disposing the first photoluminescence material over the first and second LEDs.

Abstract: Provided are a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes: a first display region and a second display region; the first display region includes a plurality of first pixels, the first pixel includes a passive light-emitting device, the second display region includes a plurality of second pixels, the second pixel includes an active light-emitting device and a pixel drive circuit electrically connected to the active light-emitting device. The first display region further includes a plurality of first cathode blockers, and the first cathode blocker includes at least one first groove, wherein the first cathode blocker is provided between at least two adjacent columns of first pixels, to make the cathodes of the two adjacent columns of first pixels disconnected.

Abstract: A connecting component, a display panel, and a display device are provided. The connecting component includes a first plane and a second plane which are perpendicular to each other. The first plane is provided with a plurality of first terminals, the second plane is provided with a plurality of second terminals corresponding to the first terminals. Each of the first terminals is connected to a corresponding second terminal by a conducting wire. The connecting component may improve display effect of the display device formed by splicing the display panels, reducing risks of wiring breakage of a chip on flex (COF).

Abstract: A micromachined ultrasonic transducers with non-coplanar actuation and displacement comprising a plate with a protruding center mass, a substrate with a center depression configured to accept the center mass, a first electrode coupled to a non-horizontal edge surface of the center mass, and a second electrode coupled to a non-horizontal edge surface of the center depression. The plate may be coupled to the substrate at least along an outer perimeter area of the plate and the substrate.

Abstract: Embodiments disclosed herein include micro light emitting device (LED) display panels and methods of forming such devices. In an embodiment, a display panel includes a display backplane substrate, a light emitting element on the display backplane, a transparent conductor over the light emitting element, a dielectric layer over the transparent conductor, and a color conversion device over the light emitting element. In an embodiment, the dielectric layer separates the transparent conductor from the color conversion device.