Patents Examined by William Bunch
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Patent number: 5047365Abstract: A heterostructure bipolar transistor is formed by a process of steps of holding an N-type gallium arsenide body using as an emitter region in a high vacuum of 10.sup.-9 torr to 10.sup.-13 torr at a first temperature of 400.degree. C. to 1,000.degree. C. where arsenic on a surface of the gallium arsenide body drifts away, lowering the first temperature to a second temperature of 300.degree. C. to 400.degree. C. to start a molecular beam epitaxial growth of a germanium, and forming an N-type germanium layer using as a collector region.Type: GrantFiled: March 27, 1989Date of Patent: September 10, 1991Assignee: NEC CorporationInventors: Masafumi Kawanaka, Jun'ichi Sone, Tooru Kimura
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Patent number: 5047364Abstract: A multi-point light emission type semiconductor laser device including a plurality of light emission points which are produced on a p type or n type semiconductor layer monolithically and are capable of being driven independently includes electrically insulating or semi-insulating semiconductor regions provided at intermediate portions of light emission points in the p type or n type semiconductor layer. A separation groove is further produced up to reaching the insulating or semi-insulating regions from the side opposite to the semiconductor layer. Thus, respective light emission points are perfectly electrically separated each other by this separation groove and the region.Type: GrantFiled: March 8, 1990Date of Patent: September 10, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Ryo Hattori
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Patent number: 5045500Abstract: A semiconductor laser includes a first cladding layer having a forward mesa with at least one end at least partially spaced from the adjacent facet of the laser. A current blocking layer buries the mesa at its sides and at least partially at the ends of the mesa so that the ends are at least partially spaced from the facets. The current blocking layer reduces current injection and surface recombination at the facets at least partially spaced from the mesa ends, thereby increasing the catastrophic optical damage level of the laser. The mesa is formed without etching or exposing the active layer so that formation of interfaces that refract light or shorten laser lifetime are avoided. An increase in COD level of about 20 percent is achieved in the invention.Type: GrantFiled: July 25, 1990Date of Patent: September 3, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeru Mitsui, Ryo Hattori, Tetsuya Yagi
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Patent number: 5045496Abstract: A process is described for growing at least one layer doped with a transition element of cobalt on a substrate by introducing a source of indium, such as tri ethyl indium, (C.sub.2 H.sub.5).sub.3 In or, a source of a group V element, a source of the transition element, such as cobalt nitrosyl tricarbonyl CO(NO)(CO).sub.3, and a source of phosphorus, to the substrate heated in an inert or reducing atmosphere at a pressure substantially between 1/100 atmosphere and one atmosphere to grow at least one semi-insulating semiconductor layer on the substrate.Type: GrantFiled: May 13, 1988Date of Patent: September 3, 1991Assignee: Rockwell International CorporationInventors: Kenneth L. Hess, Stanley W. Zehr
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Patent number: 5045499Abstract: Disclosed are a distributed Bragg reflector type semiconductor laser and a method of manufacturing such a laser a high yields, in which the upper surface of an active waveguide is covered by an external waveguide, the external waveguide at side portions thereof, the external waveguide is coupled with the edge surfaces of the active waveguide without any gap remaining, and the coupling ratio of the active waveguide and external waveguide is high.Type: GrantFiled: September 26, 1989Date of Patent: September 3, 1991Assignees: Research Development Corporation of Japan, Sumitomo Electric Industries, Ltd., Tokyo Institute of TechnologyInventors: Hideaki Nishizawa, Mitsuo Takahashi, Yasuharu Suematsu
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Patent number: 5043290Abstract: A process for forming electrodes for semiconductor devices having a semiconductor substrate and an electrically conductive portion covered and protected by an electrically insulating coating. The process includes the steps of forming an electrically conductive film on the electrically insulating coating, forming an electrode to be connected to an external circuit on the electrically conductive film at a position overlying the electrically conductive portion by exposing portions of the electrically insulating coating and the first electrically conductive film to a converged ion beam, electrically connecting the electrode to the exposed portions of the electrically conductive film, and removing the portions of the electrically conductive film not covered by the electrode. As a result, the likelihood of breakdown of the internal circuit of the semiconductor device connected to the electrically conductive portion while the electrode is being formed is greatly reduced.Type: GrantFiled: April 14, 1989Date of Patent: August 27, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadashi Nishioka, Yoji Mashiko, Hiroaki Morimoto, Hiroshi Koyama
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Patent number: 5041393Abstract: A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.Type: GrantFiled: December 28, 1988Date of Patent: August 20, 1991Assignee: AT&T Bell LaboratoriesInventors: Richard E. Ahrens, Albert G. Baca, Randolph H. Burton, Michael P. Iannuzzi, Alex Lahav, Shin-Shem Pei, Claude L. Reynolds, Jr., Thi-Hong-Ha Vuong
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Patent number: 5039626Abstract: The disclosed method at first eliminates free bonds from a crystal surface of a three-dimensional substrate by terminating severed couplers or dangling bonds on the crystal surface by coupling such atoms to them which atoms are inseparable at temperatures for ensuring heteroepitaxial growth. The crystal surface has a 6-fold or 3-fold symmetry, such as (111) plane of a crystal of cubic symmetry or (0001) plane of a crystal of hexagonal symmetry. Then, a two-dimensional material, which is a layered material having bonds closed on a superthin two-dimensional layer, is formed by evaporation on the above dangling-bond-free crystal surface of the substrate so as to cause heteroepitaxial growth while orienting atoms of the two-dimensional material in direction of crystalline axis of the substrate by van der Vaars' force.Type: GrantFiled: July 25, 1989Date of Patent: August 13, 1991Assignee: University of TokyoInventors: Atsushi Koma, Koichiro Saiki
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Patent number: 5037776Abstract: A method, and devices produced therewith, for the epitaxial growth of sub-micron semiconductor structures with at least one crystal plane-dependently grown, buried active layer (24) consisting of a III-V compound. The active layer (24) and adjacent embedding layers (23, 25) form a heterostructure produced in a one-step growth process not requiring removal of the sample from the growth chamber in between layer depositions. The layers of the structure are grown on a semiconductor substrate (21) having a structured surface exposing regions of different crystal orientation providing growth and no-growth-planes for the selective growth process. The method allows the production of multiple, closely spaced active layers and of layers consisting of adjoining sections having different physical properties.Type: GrantFiled: September 14, 1989Date of Patent: August 6, 1991Assignee: International Business Machines CorporationInventors: Yvan Galeuchet, Volker Graf, Wilhelm Heuberger, Peter Roentgen
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Patent number: 5036022Abstract: This invention is directed to a method of epitaxial growth by metal organic vapor phase epitaxy (MOVPE) of Group III-V compound semiconductors in a hot wall reactor. Epitaxy is accomplished by use of precursors having a metal, an organic ligand, and an inorganic ligand. The system is operated at very low pressures to provide a high throughput of wafers and a highly uniform deposition growth. The invention is further directed to the use of the class of precursors to selectively grow III-V compounds on a masked substrate, wherein growth occurs epitaxially on the exposed areas of the substrate but not on the surrounding mask.Type: GrantFiled: November 1, 1990Date of Patent: July 30, 1991Assignee: International Business Machines CorporationInventors: Thomas F. Kuech, Michael A. Tischler
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Method of producing a semiconductor laser adapted for use in an analog optical communications system
Patent number: 5034334Abstract: An advantageous method of fabricating lasers adapted for use in a multichannel analog optical fiber communication system, e.g., a CATV system, is disclosed. A laser generally can be used in such a communication system only if it meets, inter alia, very stringent intermodulation specifications. To identify such lasers typically requires extensive testing. It has now been discovered that certain readily determinable parameters can be used to predict the intermodulation behavior of a given device. This discovery makes possible a simpler, and therefore less costly, process of identifying suitable lasers, resulting in a more economical method of making lasers for the stated application. The method comprises measuring the light versus current (L versus I) characteristic of a given laser, determining therefrom the first, second, and possibly higher, order derivatives of L with respect to I, and determining thereform a parameter that is a predictor of the distortion behavior of the laser.Type: GrantFiled: October 13, 1989Date of Patent: July 23, 1991Assignee: AT&T Bell LaboratoriesInventors: Edward J. Flynn, Carl J. McGrath, Paul M. Nitzsche, Charles B. Roxlo -
Patent number: 5028563Abstract: A PbTe/PbEuSeTe buried heterostructure tunable diode laser and array and the method for making the same. The active region layer is buried between two lead salt semiconductor layers containing europium and selenium that are mutually of opposite conductivity type and have substantially the same lattice constant as the active region layer. In addition, the europium and selenium containing lead chalcogenide layers have an energy band gap greater than the active buried layer and an index of refraction less than the active layer. The buried structure enhances electrical and optical confinement, reduces threshold currents, and provides a stable single mode laser. Strontium, calcium or tin may be used in place of the europium. The buried laser and array are produced using a two-step molecular beam epitaxy method.Type: GrantFiled: January 23, 1990Date of Patent: July 2, 1991Assignee: Laser Photonics, Inc.Inventors: Zeev Feit, Douglas Kostyk, Robert J. Woods
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Patent number: 5028561Abstract: P-type doping of a molecular beam epitaxy (MBE) grown substrate composed of a Group II-VI combination is accomplished by forming a flux from a Group II-V combination, and applying the flux to the substrate at a pressure less than about 10.sup.-6 atmosphere. The Group II material is selected from Zn, Cd, Hg and Mg, the Group V material from As, Sb and P, and the Group VI material from S, Se and Te. The Group II-V dopant combination is preferably provided as a compound formed predominantly from the Group II material, and having the formulation X.sub.3 Y.sub.2, where X is the Group II material and Y is the Group V material. The doping concentration is controlled by controlling the temperature of the Group II-V combination. Metal vacancies in the lattice structure are tied up by the Group II constituent of the dopant combination, leaving the Group V dopant available to enter the Group VI sublattice and produce a p-type doping.Type: GrantFiled: June 15, 1989Date of Patent: July 2, 1991Assignee: Hughes Aircraft CompanyInventors: G. Sanjiv Kamath, Owen K. Wu
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Patent number: 5026660Abstract: A shadow-masking process for manufacturing low dark current photodetectors with low noise characteristics is disclosed. The process includes shadow-masking a semiconductor wafer by positioning a patterned shadow-mask on a surface of the wafer. The shadow-mask is patterned with, for example, circular openings or stripe openings. Layers, such as metallization layers to form metallic contacts or anti-reflection layers are deposited onto the wafer through the patterned openings in the shadow-masks. This shadow-masking process may be used in the production of any semiconductor device requiring patterned layers.Type: GrantFiled: September 6, 1989Date of Patent: June 25, 1991Assignee: Codenoll Technology CorporationInventors: Bulusu V. Dutt, Peter G. Abbott
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Patent number: 5026661Abstract: A method of growing zinc chalcogenide in an atmosphere which contains the vapor of di-.pi.-cyclopentadienyl manganese or di-.pi.-alkyl cyclopentadienyl manganese that serves as a source of manganese. By growing zinc chalcogenide in the above atmosphere, there is obtained a manganese-doped zinc chalcogenide having a very high crystal quality, which is very suitable for the active layer in light emitting devices.Type: GrantFiled: October 13, 1989Date of Patent: June 25, 1991Assignee: Hitachi, Ltd.Inventors: Masahito Migita, Osamu Kanehisa, Masatoshi Shiiki, Hajime Yamamoto
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Patent number: 5023198Abstract: A quaternary semiconductor diffraction grating, such as an InGaAsP grating suitable for a DFB laser, is embedded in a semiconductor substrate, such as InP. In one embodiment, the grating is fabricated by(1) forming on the top surface of an InP substrate body an epitaxial layer of InGaAsP coated with an epitaxial layer of InP;(2) forming a pattern of apertures penetrating through the layers of InP and InGaAsP; and(3) heating the body to a temperature sufficient to cause a mass transport of InP from the InP epitaxial layer, the thickness of the InP layer being sufficient to bury the entire surface of the InGaAsP layer with InP.Type: GrantFiled: February 28, 1990Date of Patent: June 11, 1991Assignee: AT&T Bell LaboratoriesInventor: Keith E. Strege
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Patent number: 5021103Abstract: A microcrystalline silicon-containing silicon carbide semiconductor film has an optical energy gap of not less than 2.0 eV, and a dark electric conductivity of less than 10.sup.-6 Scm.sup.-1. The Raman scattering light of the microcrystalline silicon-containing silicon carbide semiconductor film, which shows the presence of silicon crystal phase, has a peak in the vicinity of 530 cm.sup.-1. This microcrystalline silicon-containing silicon carbide semiconductor film is formed on a substrate by preparing a mixture gas having a hydrogen dilution rate .gamma., which is the ratio of the partial pressure of hydrogen gas to the sum of the partial pressure of a silicon-containing gas and the partial pressure of a carbon-containing gas, of 30, transmitting microwave of a frequency of not less than 100 MHz into the mixture gas near a substrate with an electric power density of not less than 4.4.times.10.sup.-2, and generating plasma at a temperature of the substrate of not less than 200.degree. C.Type: GrantFiled: May 2, 1990Date of Patent: June 4, 1991Assignees: Nippon Soken, Inc., Nippondenso Co., Ltd., Yoshihiro HamakawaInventors: Yoshihiro Hamakawa, Hiroaki Okamoto, Yutaka Hattori
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Patent number: 5021361Abstract: In a monolithic OEIC in which an FET and a light-emitting device are integrated, the light-emitting device has a first clad layer, an active layer, and a second clad layer stacked on a substrate, the FET has a channel layer and source and drain layers with a high impurity concentration stacked on the substrate, etching mask layers on the source and drain layers, and a gate electrode formed on a channel layer between source and drain electrodes and the source and drain layers, the first clad layer of the light-emitting diode and the source and drain layers with a high impurity concentration of the FET are formed of the same semiconductor layer, and an active layer of the light-emitting device and the etching mask layers of the FET are formed of the same semiconductor layer.Type: GrantFiled: December 11, 1989Date of Patent: June 4, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Jun'ichi Kinoshita, Nobuo Suzuki, Motoyasu Morinaga, Yuzo Hirayama, Masaru Nakamura
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Patent number: 5019529Abstract: A heteroepitaxial growth method wherein a III-V group compound semiconductor is formed on a silicon substrate. A first amorphous III-V group compound semiconductor layer is formed on the silicon substrate before forming a III-V group compound semiconductor crystal layer on the amorphous III-V group compound semiconductor layer. A second amorphous III-V group semiconductor layer having a thickness greater than the crystal layer is formed on the III-V group compound semiconductor crystal layer and subjected to a solid phase epitaxial growth whereby the second amorphous III-V group compound semiconductor layer is made a single crystalline layer.Type: GrantFiled: May 2, 1989Date of Patent: May 28, 1991Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 5013670Abstract: A photoelectric conversion device includes a light transmissive substrate having a deposition surface and a bottom surface. The bottom surface receives light and passes it through the substrate. A heterogeneous deposition surface is formed on the substrate deposition surface and has a nucleation density higher than the nucleation density of the substrate deposition surface. The heterogeneous deposition surface also has an area dimensioned to permit growth of a single nucleus of a single crystal material. A photoelectric conversion collector is formed of the single crystal material grown on the heterogeneous deposition surface. The collector receives light passed through the substrate bottom surface. Photoresponsive transistor elements are formed in and on the collector for outputting a signal corresponding to the light received by the collector through the bottom of the light transmissive substrate.Type: GrantFiled: May 15, 1990Date of Patent: May 7, 1991Assignee: Canon Kabushiki KaishaInventors: Shiro Arikawa, Takao Yonehara