Abstract: An insulative film, such as SiO.sub.2, Si.sub.3 N.sub.4 and PSG films, for example, is commonly used the passivation film or gate electrode of MISFETs. Stability of the insulative films during the production or operation of the semiconductor devices is enhanced by providing an insulative film which is formed by nitridation, for example, in an NH.sub.3 gas, of an SiO.sub.2 film, preferably a directly thermally oxidized film of silicon. The insulative film according to the present invention is used for a gate insulation film in MISFETs, a capacitor or passivation film for semiconductor devices, and as a mask for selectively forming circuit elements of semiconductor devices. The process for forming the insulative film may comprise successive nitridation, oxidation and nitridation steps.

Abstract: An image photodetector includes a photosensor unit, a charge storage unit, and a switch unit, all of them are formed on a single-crystal semiconductor film grown from a single nucleus such that crystal formation is performed on a substrate having a free surface including a non-nucleus formation surface and a nucleus formation surface adjacent thereto. The non-nucleus formation surface has a low nucleation density. The nucleus formation surface has a sufficiently small area to allow growth of only the single nucleus and has a higher nucleation density that that of the non-nucleus formation surface.

Abstract: The presence of oval defects on MBE-grown compound semiconductor (e.g., GaAs, InP, or InGaAs) epitaxial layers has proven to be a serious obstacle to the use of such material for the manufacture of integrated circuits (ICs), even though the use of such material potentially could result in ICs having superior performance. One particularly prevalent type of oval defect is generally referred to as .alpha.-type. It has now been discovered that compound semiconductor epitaxial layers that are essentially free of .alpha.-type oval defects can be grown by MBE if first at least a portion of the Ga and/or In metal crucible is coated with an appropriate second metal. The second metal is chosen from the group of metals that are wetted by the first metal and that are less electronegative than the first metal. Aluminum is a currently preferred second metal.

Abstract: A method of manufacturing a semiconductor device comprising at least the step of forming by a so-called method of deposition from the chloride vapour phase two superimposed epitaxial layers, the lower layer being made of a ternary compound and the upper layer being made of a binary compound, both of a semiconductor material of the III-V group, characterized in that the operating conditions of deposition temperature and molar fractions of the compounds required to form the layers are chosen so that both the lower layer of ternary material and the upper layer of binary material have before, during and after the transient state corresponding to the passage from the lower layer to the upper layer a maximum rate of coverage with chlorine (Cl) atoms.Application: hetero-structure GaInAs/InP for optoelectronic integrated circuits.

Abstract: Epitaxial Si-Ge heterostructures are formed by depositing a layer of amorphous Si-Ge on a silicon wafer. The amorphous Si-Ge on the silicon wafer is then subjected to a wet oxidation in order to form an epitaxial Si-Ge heterostructure. Any size wafer may be used and no special precaustions need be taken to ensure a clean amorphous Si-Ge/Si interface.

Abstract: A two dimensional, surface-emitting array of semiconductor lasers. Lasers disposed on a semiconductor substrate emit light in a direction substantially parallel to the substrate surface into a high index material in which the lasers are embedded. Internal reflectors composed of a low index material, also embedded in the high index material, reflect the laser beams to the surface of the array. The indexes of the low index material and the high index material are chosen so that none of the light enters the internal reflector, and all light is reflected to the laser array surface.

Abstract: A light emitting semiconducting structure is formed over a light reflecting surface using epitaxial growth techniques. The light reflecting surface is provided by an appropriate metal layer intermediately disposed between two dielectric layers, this multi-layer structure is disposed intermediate between an underlying substrate and the overlaying light emitting semiconducting components. The light reflecting surface provides enhanced photon reflectance for the light emitting device. The active region of the light emitting device is formed using epitaxial growth techniques.

Abstract: A method of manufacturing a semiconductor device in which a silicon layer (8) is epitaxially grown on the surface of a doped monocrystalline semiconductor body (7), whereafter a connection is established between said semiconductor body (7) and a second semiconductor body (1) which is used as a supporting body, while at least one of the surfaces of the two bodies is firstly provided with an insulating layer (2,3) and a rigid connection is established between the bodies, whereafter the monocrystalline semiconductor body (7) is electrochemically etched away down to the epitaxially grown silicon layer (8), parts of the insulating layer (2,3) being removed prior to establishing the connection between the bodies (1,7), whereafter a layer of electrically conducting material (6) is deposited on the surface with a thickness which is larger than that of the insulating layer, whereafter a polishing treatment is performed at least down to the insulating layer.

Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A method for simultaneously forming an epitaxial silicon layer on a surface of a silicon substrate, and a polysilicon layer on a silicon dioxide (SiO.sub.2) layer which is formed on the silicon substrate using a low pressure silicon vapor deposition method, employing silicon hydride gas, particularly disilane (Si.sub.2 O.sub.6), as a silicon source gas. A crystal growing temperature ranging from 780.degree. C. to 950.degree. C. and a reaction gas pressure ranging from 20 Torr to 300 Torr are desirable. An extended silicon epitaxial region is achieved under a higher temperature and a higher gas pressure, and with a substrate of a (100) orientation. A polysilicon layer having an even surface and joining smoothly to an epitaxial silicon layer which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate of a (111) orientation.

Abstract: A semiconductor laser device includes a current blocking structure having a p-n-p-n structure, provided on a first conductivity type semiconductor substrate, an active region buried in a stripe shaped groove produced in the current blocking structure, a lower cladding layer grown by liquid phase epitaxy approximately filling the stripe groove, an active layer on the lower cladding layer in the stripe groove, a waveguide layer on the active layer completely filling the groove, and a diffraction grating on the waveguide layer.

Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.

Abstract: An InP semiconductor thin film is formed by a process in which an amorphous GaAs buffer layer having a good surface flatness, and then an amorphous InP buffer layer having a good surface flatness are formed on an Si substrate, and then an InP monocrystalline thin film is grown on the InP buffer layer. GaAS has a lattice constant intermediate between Si used as the substrate and InP, so the lattice mismatch is reduced.

Abstract: A method of manufacturing an epitaxial InP layer on a substrate surface by means of a MOVPE process at atmospheric pressure, cyclopentadienyl indium (I) or alkyl cyclopentadienyl indium (I) being used as the indium precursor, thereby precluding side reactions.

Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.

Abstract: A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5.degree. and 5.degree. with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of the top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or mor GaP/GaAsP, GaAsP/GaAs superlattice layers. the wafer may be used to produce a seimconductor light emitting element which has a plurality of crystalline gaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer.

Abstract: In situ evaporation of selected surface regions or layers of compound semiconductors is accomplished without breaking the growth system environment employing photo induced evaporation enhancement in chemical vapor deposition epitaxy. Intense radiation from an energy source desorbs or causes evaporation of consecutive monolayers of atoms or combined atoms from the surface crystal by thermal evaporation. The desorbed atoms from the growth surface are removed atomic layer by atomic layer in a fairly uniform and systematic manner and may be characterized as "monolayer peeling" resulting in a morphology that is sculpturally smooth and molecularly continuous. In this sense, the method of this invention is analogous to erasing or the etching of crystal material and is the antithesis to laser deposition patterning wherein erasure after growth or reduced rate of growth during growth provide "negative growth patterning".

Abstract: An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer.

Abstract: A process for forming electrodes for semiconductor devices having a semiconductor substrate and an electrically conductive portion covered and protected by an electrically insulating coating. The process includes the steps of forming an electrically conductive film on the electrically insulating coating, forming an electrode to be connected to an external circuit on the electrically conductive film at a position overlying the electrically conductive portion by exposing portions of the electrically insulating coating and the first electrically conductive film to a converged ion beam, electrically connecting the electrode to the exposed portions of the electrically conductive film, and removing the portions of the electrically conductive film not covered by the electrode. As a result, the likelihood of breakdown of the internal circuit of the semiconductor device connected to the electrically conductive portion while the electrode is being formed is greatly reduced.