Abstract: A material with reduced surface defects includes a defect filter layer on an underlying material. The defect filter reduces dislocations and defects present in an underlying material. The defect filter include islands of one material formed on the underlying material and a continuous layer of a second material over the islands. The pair of layers is repeated a plurality of times to reduce the number of defects emanating from the underlying material.

Abstract: A device for emitting radiation at a predetermined wavelength is disclosed. The device has a cavity comprising a first bulk region and a second bulk region of opposite conductivity type wherein a barrier is provided for spatially separating the charge carriers of the first and the second region substantially at the antinode of the standing wave pattern of said cavity. The recombination of the charge carriers at the barrier create radiation, the emission wavelength of the radiation being determined by the cavity.

Abstract: An electronic device on a semiconductor substrate can include first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate dielectric layer having a first nitrogen concentration, and the second field effect transistor includes a second gate dielectric layer having a second nitrogen concentration lower than the first nitrogen concentration. More particularly, the first field effect transistor can be a PMOS transistor, and the second field effect transistor can be an NMOS transistor. Related methods are also discussed.

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (Vt). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A solder bump structure and a method for forming the same are disclosed. Over a contact pad a first and a second metal film are deposited, wherein the second metal film is patterned prior to the deposition of a solder bump material such that an opening isolates an inner region of the second metal film from an outer region of the second metal film. The solder material deposited on the inner region and, at least partially, in the opening serves as an etch stop for a subsequent removal of the outer region.

Abstract: Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silicon substrate 10. N-type impurities are injected into the NMOS regions (FIG. 1A). A WSi film 22 is formed on the amorphous silicon film 16, and N-type impurities are injected only into the PMOS regions of the film 16 (FIG. 1C). A silicon oxide film 28 and a silicon nitride film 30 are formed on the WSi film 22 and then etched into gate electrodes (FIG. 1E).

Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulated film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.

Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Abstract: A method of producing a semiconductor device by dividing a semiconductor wafer into separate pieces of semiconductor chips. This method includes forming a groove with a pattern according to an outer contour of a desired semiconductor chip, holding the semiconductor wafer by a wafer holding mechanism, grinding a back surface of the semiconductor wafer held by the wafer holding mechanism detecting opening of a bottom face of the groove during the back surface grinding process to determine timing for finishing the back surface grinding. The opening of the groove can be detected by means of a light sensor for detecting light passing through the groove or a microwave sensor for detecting a microwave passing through the groove. In addition, it is possible to suck air inside the groove so as to detect the opening of the groove by a pressure rise in the air inside the groove.

Abstract: A vertical color filter detector group according to the present invention is formed on a semiconductor substrate and comprises at least six layers of alternating p-type and n-typed doped regions. PN junctions between the layers operate as photodiodes with spectral sensitivities that depend on the absorption depth versus wavelength of light in the semiconductor. Alternate layers, preferably the n-type layers, are detector layers to collect photo-generated carriers, while the intervening layers, preferably p-type, are reference layers and are connected in common to a reference potential referred to as ground. Each detector group includes a blue-sensitive detector layer at an n-type layer at the surface of the semiconductor, a green-sensitive detector layer at an n-type layer deeper in the semiconductor, and a red-sensitive detector layer at the n-type layer deepest in the semiconductor.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions on a surface thereof, and a dicing line between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region; a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; and an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connecting wiring portions and at least some of the wiring pattern extends obliquely across the dicing line.

Abstract: A method of making a micro electro-mechanical switch or tunneling sensor. A cantilevered beam structure and a mating structure are defined on a first substrate or wafer; and at least one contact structure and a mating structure are defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer. A bonding layer, preferably a eutectic bonding layer, is provided on at least one of the mating structures. The mating structure of the first substrate is moved into a confronting relationship with the mating structure of the second substrate or wafer. Pressure is applied between the two substrates so as to cause a bond to occur between the two mating structures at the bonding or eutectic layer. Then the first substrate or wafer is removed to free the cantilevered beam structure for movement relative to the second substrate or wafer.

Abstract: The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

Abstract: A lens is formed out of semiconductor material. The semiconductor produces light which is coupled to the lens. The lens focuses the light and also minimizes refractive reflection. The lens is formed by a graded aluminum alloy, which is oxidized in a lateral direction. The oxidation changes the effective shape of the device according to the grading.

Abstract: A method of constructing a semiconductor device 10 is disclosed which includes a reflow step. The device 10 comprises a conductive via 20 electrically connected to a conductive interconnect 28. The formation of interconnect 28 can result in damage to conductive via 20 including the removal of material within conductive via 20 to form a void 30. The metal reflow step involves heating the structure to a temperature short of the melting point of the conductive material forming the conductive via 20 and the conductive interconnect 28. The reflow step results in the migration of conductive material into the void 30 and a widening of the conductive interface between the conductive via 20 and the conductive interconnect 28.

Abstract: In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. The material extends to above the elevational step uppermost surface and has lower and upper layers. The lower layer polishes at slower rate than the upper layer under common polishing conditions. The lower layer joins the upper layer at an interface. The material is polished down to about the elevational level of the elevational step uppermost surface utilizing the common polishing conditions. In another aspect, the invention encompasses a method of forming an isolation region. A substrate is provided. The substrate has an opening extending therein and a surface proximate the opening. A material is formed within the opening. The material extends to above the substrate surface, and comprises a lower layer and an upper layer.

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.