Abstract: A method for removing contaminant compounds respectively having a benzene ring therein from the surface of an Si layer, the method containing enter a step for causing the Si layer to contact with the air, oxygen or ozone under a heated condition or a step for causing the Si layer to contact with a mixture of sulfuric acid and hydrogen peroxide or a mixture of pure water and ozone. The method can be applicable to methods for providing a field effect transistor.

Abstract: A method of forming a boride layer for integrated circuit fabrication is disclosed. In one embodiment, the boride layer is formed by chemisorbing monolayers of a boron containing compound and one refractory metal compound onto a substrate. In an alternate embodiment, the boride layer has a composite structure. The composite boride layer structure comprises two or more refractory metals. The composite boride layer is formed by sequentially chemisorbing monolayers of a boron compound and two or more refractory metal compounds on a substrate.

Abstract: The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A process of forming a solder bump on a semiconductor device including vibrating a solder reservoir carrier in a vertical direction while pressure and heat are applied to the solder reservoir. An engagement surface of the solder reservoir is contacted with an engagement surface of the semiconductor device and the semiconductor device is vibrated in a horizontal direction to reflow a portion of the solder reservoir on the engagement surface. The solder reservoir carrier and the semiconductor device are moved away from each other so that additional solder is deposited and a solder column is grown on the semiconductor device. The solder column is cut off from the solder reservoir by vibrating the solder reservoir carrier in a horizontal direction to form a solder bump on the semiconductor device.

Abstract: A display unit capable of inhibiting moisture and gas from penetrating into a liquid crystal layer and an alignment layer also after formation of a display electrode and suppressing decomposition of a material forming the display electrode is obtained. In this display unit, an impurity-introduced layer containing an impurity element having high electronegativity is formed on the surface of an insulator film and the surface of the display electrode after formation of the display electrode. Thus, the insulator film and the display electrode are improved in effects of preventing transmission of moisture and gas also after formation of the display electrode. The impurity-introduced layer formed on the surface of the display electrode stabilizes the surface of an ITO film forming the display electrode, thereby suppressing decomposition of the ITO film.

Abstract: Disclosed is a method for forming a semiconductor assembly and the resulting assembly in which a flowable adhesive material which secures a die to a support and does not form an adhesive fillet. A flowable adhesive is deposited between the die and support so that it covers about 50 to about 90 percent of the bottom surface area of the die after the die is mounted to the support. The reduced surface coverage area prevents formation of an adhesive fillet.

Abstract: A new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.

Abstract: An interlayer insulating film (104) that is formed on a substrate(101) so as to cover TFTs(102, 103) is planarized by mechanical polishing that is typified by CMP. Pixel electrodes (106, 107) are formed on the interlayer insulating film(104) and an insulating layer(108) is formed so as to cover the pixel electrodes. The insulating layer(108) is planarized by second mechanical polishing so that the surfaces of the pixel electrodes become flush with those of resulting buried insulating layers(112, 113). Since the pixel electrode surfaces have no steps, such problems as alignment failures of a liquid crystal material and a contrast reduction due to diffused reflection of light can be prevented.

Abstract: A new method and package for the mounting of semiconductor devices. A silicon substrate serves as the device supporting medium, active semiconductor devices have been created in or on the surface of the silicon substrate. A solder plate is created over the surface of the substrate that aligns with the metal points of contact in the surface of the substrate. Semiconductor devices that have been provided with solder bumps or pin-grid arrays are connected to the solder plate. Underfill is applied to the connected semiconductor devices, the devices are covered with a layer of dielectric that is planarized. Inter-device vias are created in the layer of dielectric down to the surface of the substrate, re-routing interconnect lines are formed on the surface of the dielectric. Contact balls are connected to the re-routing lines after which the semiconductor devices that have been mounted above the silicon substrate are separated by die sawing.

Abstract: A resonant photodetector assembly (10) which uses multiple reflections of light within a photodetector (20) to convert input light into an electrical signal. The photodetector (20) includes a combination of generally planar semiconductor layers including a photodetector active layer (36) where light is converted into an electrical output. The photodetector (20) further includes a first outer electrical contact layer (34) and a second outer electrical contact layer (42). A waveguide (22) is positioned on the photodetector (20) and has a waveguide active layer (26) positioned between a pair of waveguide cladding layers (24, 28), a first end (30) for receiving input light and a second end (50) for reflecting the light. A reflector (32) is positioned on the second end (50) of the waveguide (22) at an angle relative to a line parallel to the substrate (14), where the reflector (32) reflects the light received by the first end (30) of the waveguide active layer (26) towards the photodetector (20).

Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.

Abstract: A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is removed from the array region by etching with a first etch mask. A subsequently formed insulating oxide layer is formed and removed from over the polysilicon (i.e. the support region) by etching with a second etch mask. Because the polysilicon layer is left intact only where it is needed, above the region with the planar devices, and the oxide layer is left intact only where it is needed, above the region with the vertical devices, the resulting structure has a substantially planar top surface, allowing for optional subsequent metal depositions and structuring as a wiring level.

Abstract: The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

Abstract: Described is a process for manufacturing a light emitting polymer device comprising, in one embodiment, the steps of providing a transparent or non-transparent electrode-containing substrate adapted to act as a first electrode, screen printing a light emitting polymer layer, which is composed of a light emitting polymer dissolved in a solvent, onto the hole injection layer and screen printing a hole injection layer onto the transparent electrode-containing substrate on one side of the light emitting polymer layer.

Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.

Abstract: A process of fabricating a thin film semiconductor device includes the steps of: forming a semiconducting thin film on an insulating substrate; annealing the semiconducting thin film by irradiating a laser beam thereon, thereby crystallizing the semiconducting thin film; and integratedly forming thin film transistors, each including the semiconducting thin film as an active layer, with a specific arrangement pitch. In the laser annealing step, a pulsed laser beam formed in a band-shape is intermittently irradiated onto the insulating substrate and it is simultaneously moved relative to the insulating substrate in the lateral direction with a specific movement pitch to form partially overlapping regions irradiated with the laser beam between the irradiated regions.

Abstract: A metal-to-metal antifuse disposed above and insulated from a semiconductor substrate comprises a first metal layer disposed above and insulated from the semiconductor substrate. A layer of antifuse material is disposed over and in electrical contact with the first metal layer. A second metal layer is disposed over and in electrical contact with the layer of antifuse material. At least one barrier layer comprising a layer of TaN is disposed between the layer of antifuse material and one of the first and second metal layers.

Abstract: In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliability for nitride read only memory type flash memory is improved. This invention, a substrate is provided and a zirconium oxide layer is formed on substrate by reactive magnetron sputtering and a silicon nitride layer is sandwiched between a zirconium oxide layer and a silicon oxide layer. Then, an ONO layer (oxide-nitride-oxide layer) is formed. The method is using zirconium oxide as gate dielectric can reduce leakage current, increase drain current, improve subthreshold characteristics, and electron and hole mobilities.

Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.