Abstract: Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask.

Abstract: Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH4).

Abstract: Provided is a light emitting device package and a method of fabricating the same. The light emitting device package comprises a package body having a cavity, a seed layer on a surface of the package body, a conductive layer on the seed layer, a mirror layer on the conductive layer, and a light emitting device in the cavity.

Abstract: A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween.

Abstract: Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.

Abstract: Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light.

Abstract: A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

Abstract: A display device which can be manufactured with improved material use efficiency and through a simplified manufacturing process, and a manufacturing technique thereof. A light-absorbing layer is formed, an insulating layer is formed over the light-absorbing layer, the light-absorbing layer and the insulating layer are selectively irradiated with laser light to remove an irradiated region of the insulating layer so that a first opening is formed in the insulating layer, and the light-absorbing layer is selectively removed by using the insulating layer having the first opening as a mask so that a second opening is formed in the insulating layer and the light-absorbing layer. A conductive film is formed in the second opening to be in contact with the light-absorbing layer, thereby electrically connecting to the light-absorbing layer with the insulating layer interposed therebetween.

Abstract: A buried aperture in a nitride light emitting device is described. The aperture is formed in an aperture layer, typically an amorphous or polycrystalline material over an active layer that includes a nitride material. The aperture layer material typically also includes nitride. The aperture layer is etched to create an aperture which is filled with a conducting material by epitaxial regrowth. The amorphous layer is crystallized forming an electrically resistive material during or before regrowth. The conducting aperture in the electrically resistive material is well suited for directing current into a light emitting region of the active layer.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A method for fabricating substrate-free LED chips has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through the growth substrate to the multilayer semiconductor structure, the LED chips are detached from the growth substrate while simultaneously forming surface features on the chips.

Abstract: A solid-state imaging device includes: a photoelectric converting section comprising a photo-diode; a charge storage section; a charge transfer section; a first control gate section provided between the photoelectric converting section and the charge storage section to control transfer of a signal charge from the photoelectric converting section to the charge storage section; and a second control gate section provided between the charge storage section and the charge transfer section to control transfer of the signal charge from the charge storage section to the charge transfer section. The charge storage section includes: a first region formed on a side near to the first control gate section; and a second region formed on a side near to the second control gate section and configured to have a channel potential increased more than that of the first region. The second region is configured to hold the signal charge in a pinning condition.

Abstract: A method for playing a casino poker game, including providing a chance device such as a roulette wheel or a six-sided die, a poker deck of playing cards, and a wagering surface for betting options that include options regarding a subset of a dealt poker hand as well as the full hand; receiving bets in a first playing interval; dealing a plurality of poker hands in a second playing interval; operating the chance device for determining one of the poker hands to play; exposing one card of the determined playing hand; paying winners and collecting from losers regarding the subset betting options; exposing the remaining cards of the determined hand; and paying winners and collecting from losers regarding the full hand betting options.

Abstract: Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH3 (ammonia) gas which is hydroxide gas on a substrate, the manufacturing method comprising supplying the NH3 gas in a vicinity of the substrate (for example, at a position which is separated from the substrate by a distance of 0.7-4.

Abstract: An integrated structure of MEMS device and CIS device and a fabricating method thereof includes providing a substrate having a CIS region and a MEMS region defined therein with a plurality of CIS devices positioned in the CIS region; performing a multilevel interconnect process to form a multilevel interconnect structure in the CIS region and the MEMS region and a micro-machined mesh metal in the MEMS region on a front side of the substrate; performing a first etching process to form a chamber in MEMS region in the front side of the substrate; forming a first mask pattern and a second mask pattern respectively in the CIS region and the MEMS region on a back side of the substrate; and performing a second etching process to form a plurality of vent holes connecting to the chamber on the back side of the substrate through the second mask pattern.

Abstract: In a slot machine, once a player indicates the bet amount with respect to a “continuous game”, one or a plurality of “continuous games” including unit games that are executed by the number of times which can be indicated by the player is specified through the bet amount with respect to the “continuous game” indicated by the player and the minimum bet amount with respect to a unit game which can be set by the player. Thereafter, the operation with respect to all buttons corresponding to the “continuous game” thus specified is validated. The player operates any of the buttons thus validated, whereby the “continuous game”, which is constituted of unit games executed by the number of times indicated by the player through the above-mentioned operation, is executed. Then, the bet amount with respect to the “continuous game” indicated by the player is evenly allocated to each unit game constituting the “continuous game” indicated by the player.

Abstract: In laser annealing using a solid state laser, a focus position of a minor axial direction of a rectangular beam is easily corrected depending on positional variation of a laser irradiated portion of a semiconductor film. By using a minor-axis condenser lens 29 condensing incident light in a minor axial direction and a projection lens 30 projecting light, which comes from the minor-axis condenser lens 29, onto a surface of a semiconductor film 3, laser beam 1 is condensed on the surface of the semiconductor film 3 in the minor axial direction of a rectangular beam. The positional variation of a vertical direction of the semiconductor film 3 in a laser irradiated portion of the semiconductor film 3 is detected by a positional variation detector 31, and the minor-axis condenser lens 29 is moved in an optical axis direction based on a value of the detection.

Abstract: The present invention discloses a method of manufacturing MOS device having a lightly doped drain (LDD) structure. The method includes: providing a first conductive type substrate; forming an isolation region in the substrate to define a device area; forming a gate structure in the device area, the gate structure having a dielectric layer, a stack layer, and a spacer layer on the sidewalls of the stack layer; implanting second conductive type impurities into the substrate with a tilt angle to form an LDD structure, wherein at least some of the impurities are implanted into the substrate through the spacer to form part of the LDD structure below the spacer layer; and implanting second conductive type impurities into the substrate to form source and drain.

Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.