Abstract: An embodiment relates to a light emitting device package and a lighting apparatus having the same. According to the embodiment, a light emitting device package includes a first lead frame; a second lead frame spaced apart from the first lead frame; a body coupled to the first lead frame and the second lead frame and includes a first cavity which exposes a portion of the upper surface of the first lead frame, a second cavity which exposes a portion of the upper surface of the second lead frame, and a spacer which is disposed between the first lead frame and the second frame; at least one light emitting device disposed in the first cavity; and a protection device disposed in the second cavity. The second cavity is disposed on a first inside surface of the first cavity and the first inside surface is connected to an upper surface of the spacer, and an area of a bottom surface of the first cavity is equal to or less than 40% of entire area of the body.

Abstract: According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes a free magnetic layer structure having a variable magnetization orientation, a fixed magnetic layer structure having a fixed magnetization orientation, and a tilting magnetic layer structure configured to provide an interlayer exchange biasing field to tilt, at equilibrium, the fixed magnetization orientation or the variable magnetization orientation relative to the other to be along a tilting axis that is at least substantially non-parallel to at least one of a first easy axis of the fixed magnetization orientation or a second easy axis of the variable magnetization orientation. According to further embodiments of the present invention, a method of forming a magnetoresistive device is also provided.

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

Abstract: A display apparatus is provided that includes a substrate having a display area and a peripheral area located outside the display area. A first part of an edge of the display area has a round shape and the peripheral area includes a pad area. The display apparatus further includes a first wiring extending in a direction toward the first part from the pad area, and having a first discontinuous point at which the first wiring is physically discontinuous; and a first bridge wiring allowing the first wiring to be electrically continuous at the first discontinuous point.

Abstract: A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one or more connection posts. Each connection post is in electrical contact with a connection pad. A resin is disposed between and in contact with the substrate and the component. The resin has a reflow temperature less than a cure temperature. The resin repeatedly flows at the reflow temperature when temperature-cycled between an operating temperature and the reflow temperature but does not flow after the resin is exposed to a cure temperature. A solder can be disposed on the connection post or the connection pad. After printing and reflow, the component can be tested and, if the component fails, another component is micro-transfer printed to the substrate, the resin is reflowed again, the other component is tested and, if it passes the test, the resin is finally cured.

Abstract: An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller.

Abstract: The present invention provides a silicon nitride circuit board in which metal plates are attached on front and rear sides of a silicon nitride substrate having a three-point bending strength of 500 MPa or higher, with attachment layers interposed therebetween, wherein assuming that a thickness of the metal plate on the front side is denoted by t1, and a thickness of the metal plate on the rear side is denoted by t2, at least one of the thicknesses t1 and t2 is 0.6 mm or larger, a numerical relation: 0.10?|t1?t2|?0.30 mm is satisfied, and warp amounts of the silicon nitride substrate in a long-side direction and a short-side direction both fall within a range from 0.01 to 1.0 mm. Due to above configuration, TCT properties of the silicon nitride circuit board can be improved even if the thicknesses of the front and rear metal plates are large.

Abstract: A method of manufacturing a structure includes: providing a substrate; forming an adhesive layer over the substrate; forming an interconnect layer comprising a metal line and a metal via over the adhesive layer; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars; bonding a second semiconductor die with the conductive pillars; and removing the substrate and the adhesive layer to expose a conductive portion of the interconnect layer.

Abstract: A semiconductor device includes a first electrode layer and a second electrode layer. The first electrode layer extends in a first direction. The second electrode layer extends in the first direction for a different length from the first electrode layer, and is symmetric with respect to a center line of the first electrode layer in a second direction. The second electrode layer defines a capacitor with the first electrode layer.

Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.

Abstract: A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. The method of manufacturing a display substrate includes assembling LED microparticles of each color category onto a printing template corresponding to a respective color category; the surface of the printing template being provided with assembling grooves arranged in such a manner that sub-pixels of a corresponding color category are arranged; transferring the LED microparticles on each printing template onto a same base substrate respectively to form on the base substrate an array of LED microparticles arranged in a same manner as the sub-pixels.

Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.

Abstract: A thin-film transistor (TFT) substrate includes a backing plate, a gate electrode formed on the backing plate, a gate insulation layer formed on the gate electrode and the backing plate, an active layer formed on the gate insulation layer, a source electrode and a drain electrode formed on the active layer and the gate insulation layer, a passivation layer formed on the source electrode, the drain electrode, the active layer, and the gate insulation layer, and a pixel electrode formed on the passivation layer. The gate insulation layer is formed of a material that is an oxide of a material that makes the gate electrode. The passivation layer is formed of a material that is an oxide of a material that makes the source electrode and the drain electrode.

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a source and drain of a CMOS device are formed at end portions of a channel structure by plasma doping end portions of the channel structure above solid state solubility of the channel structure, and annealing the end portions for liquid phase epitaxy and activation (e.g., superactivation). In this manner, the source and drain can be integrally formed in the end portions of the channel structure to provide coextensive surface area contact between the source and drain and the channel structure for lower channel contact resistance. This is opposed to forming the source/drain using epitaxial growth that provides an overgrowth beyond the end portion surface area of the channel structure to reduce channel contact resistance, which may short adjacent channels structures.

Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.

Abstract: A mounting structure includes a silicon die, an interposer, a substrate, and a capacitor. The capacitor includes a multilayer body, a first outer electrode provided on one end surface of the multilayer body, a second outer electrode provided on another end surface of the multilayer body, and a third outer electrode provided on side surfaces of the multilayer body, and a portion of the capacitor at the first outer electrode side is embedded within the interposer. The first outer electrode is connected to a power supply terminal of the silicon die through a via of the interposer. The second outer electrode is connected to a power supply pattern on the substrate. The third outer electrode is connected to a ground pattern within the interposer.