Patents Examined by Younes Boulghassoul
  • Patent number: 12057491
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Dax M. Crum, Stephen M. Cea, Leonard P. Guler, Tahir Ghani
  • Patent number: 12046510
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 12046658
    Abstract: Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: An-Jen B. Cheng, Brenda D. Kraus, Sanket S. Kelkar, Matthew N. Rocklein, Christopher W. Petz, Richard Beeler, Dojun Kim
  • Patent number: 12038472
    Abstract: A test site includes: at least one test module that tests a device under test; and a waveform data acquisition module that converts an electrical signal relating to the DUT into a digital signal with a predetermined sampling rate so as to acquire waveform data in the form of a digital signal sequence. The higher-level controller controls the at least one test module and the waveform data acquisition module, and collects the waveform data acquired by the waveform data acquisition module in a form associated with the operation state of the at least one test module.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 16, 2024
    Assignee: ADVANTEST CORPORATION
    Inventors: Naoya Toyota, Yasuki Akita
  • Patent number: 12033954
    Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: July 9, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, David Viveiros, Jr., Russ Alan Reisner, Robert Francis Darveaux
  • Patent number: 12034060
    Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: July 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongsik Shin, Hyunjoon Roh, Heungsik Park, Sughyun Sung, Dohaing Lee, Wonhyuk Lee
  • Patent number: 12034016
    Abstract: A first pixel circuit has a plurality of photodiodes of different sizes. A second pixel circuit is connected to the first pixel circuit, and has a holding portion that holds a first optical signal and a second optical signal. The peripheral circuit drives and controls the second pixel circuit, and determines whether a voltage value of the first optical signal is equal to or greater than a predetermined value. When it is determined that the voltage value of the first optical signal is equal to or greater than the predetermined value, a signal obtained by adding the second optical signal to the first optical signal is set as an output signal. When it is determined that the voltage value of the first optical signal is less than the predetermined value, the first optical signal is set as an output signal.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: July 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Masaki Funaki
  • Patent number: 12034007
    Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 12014986
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu).
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 18, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Te Kuo
  • Patent number: 12014957
    Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
  • Patent number: 12009300
    Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: June 11, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonggil Lee, Sukhoon Kim, Sungmyong Park, Chanyang Lee, Honyun Park
  • Patent number: 12010830
    Abstract: A method for forming a semiconductor structure and a semiconductor structure. The method includes: a semiconductor base which has a substrate and a first oxide material layer arranged on the substrate is provided. Pattern etching is performed on the first oxide material layer, to remove the first oxide material layer in the second region and that in a part of the first region, and the remaining first oxide material layer forms oxide line structures on both sides of each bit line structure; a second material is backfilled, to form an isolation line structure in the first region and a dummy isolation structure in the second region; remove the oxide line structures are removed, the bit line structures and the isolation line structures on both sides jointly form through hole structures exposing the substrate; and a conductive material layer is formed in the through hole structures to form the semiconductor structure.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: June 11, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Wenli Chen, Ming-Pu Tsai
  • Patent number: 12009408
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 12009308
    Abstract: A semiconductor chip according to an embodiment includes a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface, first and second through electrodes penetrating the body portion with protrusions that protrude above the rear surface of the body portion, a wiring portion formed under the front surface of the body portion, a power pattern formed over the rear surface of the body portion and spaced apart from the protrusions, an interlayer insulating layer filling spaces between the power pattern and the protrusions, and first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second through electrodes, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a part of the power pattern that is adjacent to the first through electrode.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: June 11, 2024
    Assignee: SK hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 12009274
    Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 11, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eungkyu Kim, Kyounglim Suk
  • Patent number: 12002766
    Abstract: A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having fin structures. The substrate includes a material having a substrate thermal expansion coefficient. The semiconductor structure also includes an isolation structure between the fin structures. The isolation structure includes a first dielectric material and a second dielectric material. The first dielectric material has a first thermal expansion coefficient and the second dielectric material has a second thermal expansion coefficient. The substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Sheng Huang, Ryan Chia-Jen Chen
  • Patent number: 12002686
    Abstract: A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 4, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Satoshi Tsukiyama, Satoru Takaku, Yuki Sugo, Ayana Amano
  • Patent number: 11996317
    Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kai Hsiao, Han-De Chen, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11990498
    Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermoconforms. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: May 21, 2024
    Assignee: Meridian Innovation Pte Ltd
    Inventors: Wan Chia Ang, Piotr Kropelnicki, Ilker Ender Ocak, Paul Simon Pontin
  • Patent number: 11984355
    Abstract: A method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. A bottom via is selectively deposited in the opening and over the metal layer. A barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. A top via is formed in the opening, in contact with the barrier layer, and over the bottom via. The top via is separated from the dielectric layer by the barrier layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan Ho, Chia-Tien Wu