Abstract: The present technology relates to a solid-state image sensing device capable of restricting a deterioration in photoelectric conversion characteristic of a photoelectric conversion unit, and an electronic device. A solid-state image sensing device includes: a photoelectric conversion unit formed outside a semiconductor substrate; a charge holding unit for holding signal charges generated by the photoelectric conversion unit; a reset transistor for resetting the potential of the charge holding unit; a capacitance switching transistor connected to the charge holding unit and directed for switching the capacitance of the charge holding unit; and an additional capacitance device connected to the capacitance switching transistor. The present technology is applicable to solid-state image sensing devices and the like, for example.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: An electronic device is provided. The electronic device includes a driving substrate, a plurality of light-emitting units, and a protective layer. The light-emitting units are electrically connected to the driving substrate. The protective layer covers the light-emitting units, and the protective layer has a Young's modulus less than or equal to 20 MPa.

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

Abstract: A light-emitting device includes: a base member including: a first lead, a second lead, and a securing member securing the first and second leads; a light-emitting element mounted on an upper surface of the base member; a frame, a part of which is disposed on the upper surface of the base member to surround the light-emitting element; a first member covering at least a portion of an upper surface of the securing member that is exposed at an outer peripheral side of the frame in a top view, the first member being arranged intermittently under the frame and containing a reflective material; and a second member covering the light-emitting element, the frame, and the first member. The frame has a first region on which the first member is arranged and a second region on which the first member is not arranged, the first and second regions having different heights.

Abstract: An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Abstract: A semiconductor device includes a substrate having a first region and a second region. A device isolation layer is disposed in the substrate between the first region and the second region. The device isolation layer includes a buried dielectric layer in a trench that is recessed from a top surface of the substrate. A first liner layer is between the trench and the buried dielectric layer. A semiconductor layer is disposed on a top surface of the substrate of the first region. A first gate pattern is disposed on the semiconductor layer. A protrusion is disposed on a top surface of the device isolation layer.

Abstract: A semiconductor storage device includes a substrate, a first conductor layer, a plurality of second conductor layers, and a first contact. The substrate includes a core region, a first region surrounding the core region, and a second region connecting the core region and the first region. The first conductor layer is above the core region, the first region, and the second region. The second conductor layers are above the first conductor layer above the core region. The first contact is above the first region and extends in the thickness direction. The first contact separates the first conductor layer above the first region into a first portion surrounded by the first contact and a second portion surrounding the first contact. The first portion of the first conductor layer includes a first oxidized portion, and the second portion of the first conductor layer includes a second oxidized portion.

Abstract: The present disclosure provides an OLED display device, a display panel and a manufacturing method of the OLED display device, and belongs to the field of display technology. The OLED display device includes a light-emitting layer, a material of the light-emitting layer includes a host light-emitting material and a carrier balance material doped in the host light-emitting material; and the carrier balance material is used for balancing an electron mobility and a hole mobility of the light-emitting layer.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

Abstract: The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: Provided is a compound of Chemical Formula 1: HAr-L1-L2-Ar1??Chemical Formula 1 wherein: HAr is a group of the following Chemical Formula A-1 or A-2; L1 and L2 are the same as or different from each other, and each independently is a direct bond, a substituted or unsubstituted monocyclic or polycyclic arylene group, or a substituted or unsubstituted monocyclic or polycyclic heteroarylene group; and Ar1 is a substituted or unsubstituted monocyclic or polycyclic aryl group, or a substituted or unsubstituted monocyclic or polycyclic heteroaryl group; wherein: R1 to R3 are the same as or different from each other, and each independently is a substituted or unsubstituted linear or branched alkyl group; and is a site bonding to L1 of Chemical Formula 1, and an organic light emitting device comprising the same.

Abstract: A semiconductor device includes a semiconductor layer, a first conductor disposed on the semiconductor layer, a second conductor disposed on the semiconductor layer so as to be separated from the first conductor, a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region, a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor, and a second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Abstract: The present specification relates to a hetero-cyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.

Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. A fin structure is formed on the substrate, and a dielectric layer is formed over the fin structure. A sacrificial gate is formed over the substrate. A portion of the dielectric layer is exposed through the sacrificial gate. Recesses are formed in the fin structure at two sides of the sacrificial gate. A cleaning operation is performed with an HF-containing plasma. The HF-containing plasma includes HF and NH3.