Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

Abstract: A method for forming a stacked semiconductor nanowire field effect transistor (FET) having reduced parasitic capacitance is provided. The parasitic capacitance of the stacked semiconductor nanowire FET including vertically stacked and vertically spaced apart semiconductor nanowires can be reduced by forming a tunnel spacer laterally surrounding a gate structure located beneath each of the vertically stacked and vertically spaced apart semiconductor nanowires.

Abstract: A substrate processing apparatus includes at least one process module configured to process first substrates. A position detector is configured to detect first positions of the first substrates. A control unit is configured to control the position detector so as to measure a second position of a second substrate selected from the first substrates to be processed in a same process module depending on a measurement interval set for the same process module.

Abstract: There is provided a method for transforming an electronic device from an initial state, wherein the device includes a first substrate and a second substrate, the first and second substrates being joined by means of a bonding interfaced using their respective first faces, wherein the first substrate includes at least one cavity, produced using the first face of the first substrate, the cavity including a bottom bordered by at least one peripheral region and being at least partially filled with a buffer layer, in the bottom of the cavity, and wherein the first face of the second substrate is at least partly opposite the cavity of the first substrate. The method also includes a step of removing the bottom of the cavity of the first substrate from a first face, opposite to the first face of the first substrate.

Abstract: A flexible fingerprint sensor laminate comprising: a layer of flexible substrate having a front surface and a back surface, at least a domain of electrically conductive material deposited on the front surface, a protective hard coating layer that covers the domain of electrically conductive material, and a plurality of sensor electrodes deposited preferably on the back surface and related circuitry (e.g. integrated circuit for driving and sensing). Preferably, the layer of flexible substrate is no greater than 20 ?m in thickness, the domain of electrically conductive material has a thickness no greater than 2 ?m, the protective hard coating has a thickness no greater than 1 ?m, and the laminate has a surface sheet resistance no greater than 200 Ohm per square and surface scratch resistance no less than 3 H. The laminate exhibits good scratch resistance, low sheet resistance, good flexibility and mechanical integrity. The invention also provides a biometric sensor, such as a fingerprint sensor.

Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Abstract: Methods and systems for forming a layer from a fluid mixture on a web are provided. The system includes a fluid delivery apparatus for delivering the fluid mixture onto the web. The fluid delivery apparatus includes a cascade device and a chemical dispenser device. The system also includes a fluid stirring apparatus comprising at least one fan positioned over the web and configured to generate a flow pattern that stirs the fluid mixture on the web while the layer is being formed, without the at least one fan contacting the fluid mixture. The system further includes a fluid removal apparatus having a rinsing device and a suction device. The rinsing device is configured to dispense a rinsing fluid onto the web. The suction device is configured to remove by suction the rinsing fluid and a remaining portion of the fluid mixture remaining on the web after formation of the layer.

Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having an insulating film and a plurality of conductive films on a surface; reducing the substrate by supplying a first reducing gas to the substrate so that at least one of a plurality of process conditions of the first reducing gas is controlled so that a product of a plurality of process conditions becomes a predetermined value, wherein the process conditions of the first reducing gas include a partial pressure of the first reducing gas in a region where the substrate exists and a time taken to supply the first reducing gas to the substrate corresponding to a temperature of the first reducing gas; and selectively forming a metal film on the plurality of the reduced conductive films by supplying a second reducing gas and a metal-containing gas to the substrate.

Abstract: One object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, which has stable electrical characteristics. In a method for manufacturing a semiconductor device, a first insulating film is formed; source and drain electrodes and an oxide semiconductor film electrically connected to the source and drain electrodes are formed over the first insulating film; heat treatment is performed on the oxide semiconductor film so that a hydrogen atom in the oxide semiconductor film is removed; oxygen doping treatment is performed on the oxide semiconductor film, so that an oxygen atom is supplied into the oxide semiconductor film; a second insulating film is formed over the oxide semiconductor film; and a gate electrode is formed over the second insulating film so as to overlap with the oxide semiconductor film.

Abstract: A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first layers and second layers that are alternately formed. The substrate has a memory region extending in first and second directions along a surface of the substrate, a step region adjacent to the memory region in the first direction, and a peripheral region adjacent to the memory region and the step region in the second direction. The insulating layers and the wiring layers are formed on the memory region and the step region. The first and second layers are formed on the peripheral region. Each of the first layers is formed on a same level as and in contact with one of the insulating layers, and each of the second layers is formed on a same level as and in contact with one of the wiring layers.

Abstract: A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.

Abstract: A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure.

Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.

Abstract: In accordance with this disclosure, there are provided several inventions, including a substrate processing apparatus with multi-layer surfaces configured to face the plasma and resist against corrosion. These multi-layer surfaces may in one example include a base layer of aluminum, anodized aluminum, or quartz, a second layer of stabilized zirconia, and a second layer of a yttrium-aluminum composite such as yttrium aluminum garnet (YAG).

Abstract: A substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer.

Abstract: A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of pads. The micro light emitting chips are disposed on the substrate in dispersion. Each of the micro light emitting chips includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer. The conductive bumps are disposed corresponding to the micro light emitting chips and located between the micro light emitting chips and the substrate. The micro light emitting chips are electrically connected to the pads of the substrate by the conductive bumps. An orthogonal projection area of each of the conductive bumps on the substrate is greater than an orthogonal projection area of each of the micro light emitting chips on the substrate.

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract: The present invention is a method for manufacturing a bonded SOI wafer including: performing a thermal oxidation treatment including at least one of a thermal oxidation during temperature-rising and a thermal oxidation during temperature-falling with the use of a batch type heat treatment furnace, thereby forming a silicon oxide film in such a way that the oxide film buried in the delaminated bonded SOI wafer has a concentric oxide film thickness distribution, and subjecting the bonded SOI wafer after delaminating a bond wafer to a reducing heat treatment to make a film thickness range of the buried oxide film being smaller than a film thickness range before the reducing heat treatment. This provides a method for manufacturing a bonded SOI wafer which can suppress a variation of a radial distribution of a buried oxide film thickness caused by a reducing heat treatment performed after delaminating the SOI layer.

Abstract: A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal.